ICS1562BM-201-4 Datasheet ICS1562BM-201, ICS1562BM-201-4, ICS1562BM-201-4LF | P4-P6

Pipeline Delay Reset Function

The ICS1562B implements the clocking sequence required to

reset the pipeline delay on Brooktree RAMDACs when the

LOAD output is programmed for a modulus of either 3, 4, 5,

6, 8 or 10. This sequence can be generated by setting the

appropriate register bit (DACRST) to a logic 1 and then reset-

ting to logic 0.

When changing frequencies, it is advisable to allow 500 mi-

croseconds after the new frequency is selected to activate the

reset function. The output frequency of the synthesizer should

be stable enough at that point for the video DAC to correctly

execute its reset sequence. See Figure 4 for a diagram of the

pipeline delay reset sequence.

Reference Oscillator and Crystal

Selection

The ICS1562B has circuitry on-board to implement a Pierce

oscillator with the addition of only one external component, a

quartz crystal. Pierce oscillators operate the crystal in anti-

(also called parallel-) resonant mode. See the AC Charac-

teristics for the effective capacitive loading to specify when

ordering crystals.

Series-resonant crystals may also be used with the ICS1562B.

Be aware that the oscillation frequency will be slightly higher

than the frequency that is stamped on the can (typically 0.025-

0.05%).

As the entire operation of the phase-locked loop depends on

having a stable reference frequency, we recommend that the

crystal be mounted as closely as possible to the package. Avoid

routing digital signals or the ICS1562B outputs underneath or

near these traces. It is also desirable to ground the crystal can

to the ground plane, if possible.

If an external reference frequency source is to be used with the

ICS1562B. it is important that it be jitter-free. The rising and

falling edges of that signal should be fast and free of noise for

best results.

The loop phase is locked to the falling edges of the XTAL1

input signals if the REFPOL bit is set to logic 0.

Internal Feedback

The ICS1562B supports LOAD (N1) and N2 divider

chains to act as the feedback divider for the PLL.

The N1 and N2 divider chains allow a much larger modulus to

be achieved than the PLL’s own feedback divider. Additionally,

the output of the N2 counter is accessible off-chip for perform-

ing horizontal reset of the graphics system, where necessary.

This mode is set under register control (ALTLOOP bit). The

reference divider (R counter) will ordinarily be set to divide by

1 in this mode, and the reference input will be supplied to

the XTAL1 input. The output frequency of the synthesizer

will then be:

(CLK)

: = F (XTAL1)

N2.

By using the phase-detector hardware disable mode, the PLL

can be made to free-run at the beginning of the vertical interval

of the external video, and can be reactivated at its completion.

ICS1562B-001 The ICS1562B-001 supports phase detector

disable via a special control mode. When the

PDRSTEN (phase detector reset enable) bit is

set and the last address latched is 15 (0Fh), a

high level on AD3 will disable PLL locking.

ICS1562B-201 The ICS1562B-201 supports phase detector

disable via the BLANK pin. When the

PDRSTEN bit is set, a high level on the

BLANK input will disable PLL locking.

Pipeline Delay Reset Timing

STROBE

DATCLK

CLK+

LOAD

CLK

Figure 4

ICS1562B

External Feedback Operation

The ICS1562B-201 option also supports the inclusion of an

external counter as the feedback divider of the PLL. This mode

is useful in graphic systems that must be “genlocked” to

external video sources.

When the EXTFBEN bit is set to logic 1, the phase-frequency

detector will use the EXTFBK pin as its feedback input. The

loop phase will be locked to the rising edges of the signal applied

to the EXTFBK input if the FBKPOL bit is set to logic 0.

VRAM Shift Clock Generation

The ICS1562B-201 option supports VRAM shift clock gen-

eration and interruption. By programming the N2 counter to

divide by 1, the LD/N2 output becomes a duplicate of the

LOAD output. When the SCEN bit is set, the LD/N2 output

may be synchronously started and stopped via the blank pin.

When BLANK is high, the LD/N2 will be free-running and in

phase with LOAD. When BLANK is taken low, the LD/N2

output is stopped at a low level. See Figure 5 for a diagram of

the sequence. Note that this use of the BLANK pin precludes its

use for phase comparator disable (see Line-Locked Operation).

Power-On Initialization

The ICS1562B has an internal power-on reset circuit that

performs the following functions:

1) Sets the multiplexer to pass the reference frequency

to the CLK+ and CLK- outputs.

2) Selects the modulus of the N1 divider (for the

LOAD clock) to be four.

These functions should allow initialization of most graphics

systems that cannot immediately provide for register program-

ming upon system power-up.

Because the power-on reset circuit is on the VDD supply, and

because that supply is filtered, care must be taken to allow the

reset to de-assert before programming. A safe guideline is to

allow 20 microseconds after the VDD supply reaches 4 volts.

Programming Notes

• VCO Frequency Range: Use the post-divider to keep the

VCO frequency as high as possible within its operating

range.

• Divider Range: For best results in normal situations (i.e,

pixel clock generation for hi-res displays), keep the refer-

ence divider modulus as short as possible (for a frequency

at the output of the reference divider in the few hundred

kHz to several MHz range). If you need to go to a lower

phase comparator reference frequency (usually required

for increased frequency accuracy), that is acceptable, but

jitter performance will suffer somewhat.

• VCO Gain Programming: Use the minimum gain which

can reliably achieve the VCO frequency desired, as shown

on the following page:

VRAM Shift Clock Control

BLANK

LOAD

LD/N2

Figure 5

ICS1562B

Figure 6

VCO GAIN MAX FREQUENCY

4 120 MHz

5 200 MHz

6 260 MHz

*SPECIAL APPLICATION. Contact factory for custom product above

260 MHz.

• Phase Detector Gain: For most graphics applications and

divider ranges, set P[1, 0] = 10 and set P[2] = 1. Under

some circumstances, setting the P[2] bit “on” can reduce

jitter. During 1562 operation at exact multiples of the

crystal frequency, P[2] bit = 0 may provide the best jitter

performance.

Board Test Support

It is often desirable to statically control the levels of the output

pins for circuit board test. The ICS1562B supports this through

a register programmable mode, AUXEN. When this mode is

set, two register bits directly control the logic levels of the

CLK+/CLK- pins and the LOAD pin. This mode is activated

when the S[0] and S[1] bits are both set to logic 1. See Register

Mapping for details.

Power Supplies and Decoupling

The ICS1562B has two VSS pins to reduce the effects of

package inductance. Both pins are connected to the same

potential on the die (the ground bus). BOTH of these pins

should connect to the ground plane of the video board as close

to the package as is possible.

The ICS1562B has a VDDO pin which is the supply of +5 volt

power to all output drivers. This pin should be connected to the

power plane (or bus) using standard high-frequency decou-

pling practice. That is, capacitors should have low series induc-

tance and be mounted close to the ICS1562B.

The VDD pin is the power supply pin for the PLL synthesizer

circuitry and other lower current digital functions. We recom-

mend that RC decoupling or zener regulation be provided for

this pin (as shown in the recommended application circuitry).

This will allow the PLL to “track” through power supply

fluctuations without visible effects. See Figure 6 for typical

external circuitry.

ICS1562B

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