Register Mapping - ICS1562B-001 (Parallel Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1562B. PC SOFTWARE IS AVAILABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.
REG# BIT(S) BIT REF. DESCRIPTION
0 0-3 R[0]..R[3] Reference divider modulus control bits
1 0-2 R[4]..R[6] Modulus = value + 1
1 3 REFPOL PLL locks to the rising edge of XTAL1 input when REFPOL=1 and
to the falling edge of XTAL1 when REFPOL=0.
2 0-3 A[0]..A[3] Controls A counter. When set to zero, modulus=7. Otherwise,
modulus=7 for “value” underflows of the prescaler, and modulus=6
thereafter until M counter underflows.
3 0-3 M[0]..M[3] M counter control bits
4 0-1 M[4]..M[5] Modulus = value + 1
4 2 FBKPOL External feedback polarity control bit. The PLL will lock to the falling
edge of EXTFBK when FBKPOL=1 and to the rising edge of
EXTFBK when FBKPOL=0.
4 3 DBLFREQ Doubles modulus of dual-modulus prescaler (from 6/7 to 12/14).
5 0-3 N1[0]..N1[3] Sets N1 modulus according to this table. These bits are set to imple-
ment a divide-by-four on power-up.
N1[3] N1[2] N1[1] N1[0] RATIO
00003
00014
00104
00115
01006
01018
01108
011110
1X0012
1X0116
1X1016
1X1120
X=Don’t Care
ICS1562B
8
