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LPC2220FET144/G,51

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 10 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
P0.28/AIN1/
CAP0.2/MAT0.2
25
[4]
J1
[4]
I AIN1 — ADC, input 1. This analog input is always connected
to its pin.
I CAP0.2 — Capture input for Timer 0, channel 2.
O MAT0.2 — Match output for Timer 0, channel 2.
P0.29/AIN2/
CAP0.3/MAT0.3
32
[4]
L1
[4]
I AIN2 — ADC, input 2. This analog input is always connected
to its pin.
I CAP0.3 — Capture input for Timer 0, Channel 3.
O MAT0.3 — Match output for Timer 0, channel 3.
P0.30/AIN3/
EINT3/CAP0.0
33
[4]
L2
[4]
I AIN3 — ADC, input 3. This analog input is always connected
to its pin.
I EINT3 — External interrupt 3 input.
I CAP0.0 — Capture input for Timer 0, channel 0.
P1.0 to P1.31 I/O Port 1: Port 1 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 1 pins
depends upon the pin function selected via the Pin Connect
Block.
Pins 0 through 15 of port 1 are not available.
P1.0/
CS0 91
[5]
G11
[5]
O CS0 — LOW-active Chip Select 0 signal.
(Bank 0 addresses range 0x8000 0000 to 0x80FF FFFF)
P1.1/
OE 90
[5]
G13
[5]
O OE — LOW-active Output Enable signal.
P1.16/
TRACEPKT0
34
[5]
L3
[5]
O TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with
internal pull-up.
P1.17/
TRACEPKT1
24
[5]
H4
[5]
O TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with
internal pull-up.
P1.18/
TRACEPKT2
15
[5]
F2
[5]
O TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with
internal pull-up.
P1.19/
TRACEPKT3
7
[5]
D2
[5]
O TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with
internal pull-up.
P1.20/
TRACESYNC
102
[5]
D12
[5]
O TRACESYNC — Trace Synchronization. Standard I/O port
with internal pull-up.
Note: LOW on this pin while
RESET is LOW, enables pins
P1[25:16] to operate as Trace port after reset.
P1.21/
PIPESTAT0
95
[5]
F11
[5]
O PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with
internal pull-up.
P1.22/
PIPESTAT1
86
[5]
H11
[5]
O PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with
internal pull-up.
P1.23/
PIPESTAT2
82
[5]
J11
[5]
O PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with
internal pull-up.
P1.24/
TRACECLK
70
[5]
L11
[5]
O TRACECLK — Trace Clock. Standard I/O port with internal
pull-up.
P1.25/EXTIN0 60
[5]
K8
[5]
I EXTIN0 — External Trigger Input. Standard I/O with internal
pull-up.
Table 4. Pin description
…continued
Symbol Pin (LQFP) Pin (TFBGA) Type Description
LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 11 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
P1.26/RTCK 52
[5]
N6
[5]
I/O RTCK — Returned Test Clock output. Extra signal added to
the JTAG port. Assists debugger synchronization when
processor frequency varies. Bidirectional pin with internal
pull-up.
Note: LOW on this pin while
RESET is LOW, enables pins
P1[31:26] to operate as Debug port after reset.
P1.27/TDO 144
[5]
B2
[5]
O TDO — Test Data out for JTAG interface.
P1.28/TDI 140
[5]
A3
[5]
I TDI — Test Data in for JTAG interface.
P1.29/TCK 126
[5]
A7
[5]
I TCK — Test Clock for JTAG interface. This clock must be
slower than
1
⁄
6
of the CPU clock (CCLK) for the JTAG interface
to operate.
P1.30/TMS 113
[5]
D10
[5]
I TMS — Test Mode Select for JTAG interface.
P1.31/
TRST 43
[5]
M4
[5]
I TRST — Test Reset for JTAG interface.
P2.0 to P2.31 I/O Port 2 — Port 2 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 2 pins
depends upon the pin function selected via the Pin Connect
Block.
P2.0/D0 98
[5]
E12
[5]
I/O D0 — External memory data line 0.
P2.1/D1 105
[5]
C12
[5]
I/O D1 — External memory data line 1.
P2.2/D2 106
[5]
C11
[5]
I/O D2 — External memory data line 2.
P2.3/D3 108
[5]
B12
[5]
I/O D3 — External memory data line 3.
P2.4/D4 109
[5]
A13
[5]
I/O D4 — External memory data line 4.
P2.5/D5 114
[5]
C10
[5]
I/O D5 — External memory data line 5.
P2.6/D6 115
[5]
B10
[5]
I/O D6 — External memory data line 6.
P2.7/D7 116
[5]
A10
[5]
I/O D7 — External memory data line 7.
P2.8/D8 117
[5]
D9
[5]
I/O D8 — External memory data line 8.
P2.9/D9 118
[5]
C9
[5]
I/O D9 — External memory data line 9.
P2.10/D10 120
[5]
A9
[5]
I/O D10 — External memory data line 10.
P2.11/D11 124
[5]
A8
[5]
I/O D11 — External memory data line 11.
P2.12/D12 125
[5]
B7
[5]
I/O D12 — External memory data line 12.
P2.13/D13 127
[5]
C7
[5]
I/O D13 — External memory data line 13.
P2.14/D14 129
[5]
A6
[5]
I/O D14 — External memory data line 14.
P2.15/D15 130
[5]
B6
[5]
I/O D15 — External memory data line 15.
P2.16/D16 131
[5]
C6
[5]
I/O D16 — External memory data line 16.
P2.17/D17 132
[5]
D6
[5]
I/O D17 — External memory data line 17.
P2.18/D18 133
[5]
A5
[5]
I/O D18 — External memory data line 18.
P2.19/D19 134
[5]
B5
[5]
I/O D19 — External memory data line 19.
P2.20/D20 136
[5]
D5
[5]
I/O D20 — External memory data line 20.
P2.21/D21 137
[5]
A4
[5]
I/O D21 — External memory data line 21.
P2.22/D22 1
[5]
A1
[5]
I/O D22 — External memory data line 22.
P2.23/D23 10
[5]
E3
[5]
I/O D23 — External memory data line 23.
P2.24/D24 11
[5]
E2
[5]
I/O D24 — External memory data line 24.
P2.25/D25 12
[5]
E1
[5]
I/O D25 — External memory data line 25.
Table 4. Pin description
…continued
Symbol Pin (LQFP) Pin (TFBGA) Type Description
LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 12 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
P2.26/D26/
BOOT0
13
[5]
F4
[5]
I/O D26 — External memory data line 26.
I BOOT0 — While
RESET is LOW, together with BOOT1
controls booting and internal operation. Internal pull-up
ensures HIGH state if pin is left unconnected.
P2.27/D27/
BOOT1
16
[5]
F1
[5]
I/O D27 — External memory data line 27.
I BOOT1 — While
RESET is LOW, together with BOOT0
controls booting and internal operation. Internal pull-up
ensures HIGH state if pin is left unconnected.
BOOT1:0 = 00 selects 8-bit memory on CS0 for boot.
BOOT1:0 = 01 selects 16-bit memory on
CS0 for boot.
BOOT1:0 = 10 selects 32-bit memory on
CS0 for boot.
BOOT1:0 = 11 selects 16-bit memory on
CS0 for boot.
P2.28/D28 17
[5]
G2
[5]
I/O D28 — External memory data line 28.
P2.29/D29 18
[5]
G1
[5]
I/O D29 — External memory data line 29.
P2.30/D30/
AIN4
19
[2]
G3
[2]
I/O D30 — External memory data line 30.
I AIN4 — ADC, input 4. This analog input is always connected
to its pin.
P2.31/D31/
AIN5
20
[2]
G4
[2]
I/O D31 — External memory data line 31.
I AIN5 — ADC, input 5. This analog input is always connected
to its pin.
P3.0 to P3.31 I/O Port 3 — Port 3 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 3 pins
depends upon the pin function selected via the Pin Connect
Block.
P3.0/A0 89
[5]
G12
[5]
O A0 — External memory address line 0.
P3.1/A1 88
[5]
H13
[5]
O A1 — External memory address line 1.
P3.2/A2 87
[5]
H12
[5]
O A2 — External memory address line 2.
P3.3/A3 81
[5]
J10
[5]
O A3 — External memory address line 3.
P3.4/A4 80
[5]
K13
[5]
O A4 — External memory address line 4.
P3.5/A5 74
[5]
M13
[5]
O A5 — External memory address line 5.
P3.6/A6 73
[5]
N13
[5]
O A6 — External memory address line 6.
P3.7/A7 72
[5]
M12
[5]
O A7 — External memory address line 7.
P3.8/A8 71
[5]
N12
[5]
O A8 — External memory address line 8.
P3.9/A9 66
[5]
M10
[5]
O A9 — External memory address line 9.
P3.10/A10 65
[5]
N10
[5]
O A10 — External memory address line 10.
P3.11/A11 64
[5]
K9
[5]
O A11 — External memory address line 11.
P3.12/A12 63
[5]
L9
[5]
O A12 — External memory address line 12.
P3.13/A13 62
[5]
M9
[5]
O A13 — External memory address line 13.
P3.14/A14 56
[5]
K7
[5]
O A14 — External memory address line 14.
P3.15/A15 55
[5]
L7
[5]
O A15 — External memory address line 15.
P3.16/A16 53
[5]
M7
[5]
O A16 — External memory address line 16.
P3.17/A17 48
[5]
N5
[5]
O A17 — External memory address line 17.
P3.18/A18 47
[5]
M5
[5]
O A18 — External memory address line 18.
Table 4. Pin description
…continued
Symbol Pin (LQFP) Pin (TFBGA) Type Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

LPC2220FET144/G,51

Mfr. #:
Buy LPC2220FET144/G,51
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 64KR/ADC/EX BUS ROMLESS
Lifecycle:
New from this manufacturer.
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