OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LPC2220FET144/G,51

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 37 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
9. Dynamic characteristics
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Bus capacitance C
b
in pF, from 10 pF to 400 pF.
Table 13. Dynamic characteristics
T
amb
=0
°
Cto+70
°
C for commercial applications,
−
40
°
C to +85
°
C for industrial applications, V
DD(1V8)
, V
DD(3V3)
over
specified ranges.
[1]
Symbol Parameter Conditions Min Typ Max Unit
External clock
f
osc
oscillator frequency supplied by an external
oscillator (signal generator)
1 - 25 MHz
external clock frequency
supplied by an external
crystal oscillator
1 - 25 MHz
external clock frequency if
on-chip PLL is used
10 - 25 MHz
external clock frequency if
on-chip bootloader is used
for initial code download
10 - 25 MHz
T
cy(clk)
clock cycle time 20 - 1000 ns
t
CHCX
clock HIGH time T
cy(clk)
× 0.4 - - ns
t
CLCX
clock LOW time T
cy(clk)
× 0.4 - - ns
t
CLCH
clock rise time - - 5 ns
t
CHCL
clock fall time - - 5 ns
Port pins (except P0.2 and P0.3)
t
r
rise time - 10 - ns
t
f
fall time - 10 - ns
I
2
C-bus pins (P0.2 and P0.3)
t
f
fall time V
IH
to V
IL
[2]
20 + 0.1 × C
b
--ns
LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 38 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
Table 14. External memory interface dynamic characteristics
C
L
= 25 pF; T
amb
=40
°
C.
Symbol Parameter Conditions Min Typ Max Unit
Common to read and write cycles
t
CHAV
XCLK HIGH to address valid
time
- - 10 ns
t
CHCSL
XCLK HIGH to CS LOW time - - 10 ns
t
CHCSH
XCLK HIGH to CS HIGH
time
- - 10 ns
t
CHANV
XCLK HIGH to address
invalid time
- - 10 ns
Read cycle parameters
t
CSLAV
CS LOW to address valid
time
[1]
−5 - +10 ns
t
OELAV
OE LOW to address valid
time
[1]
−5 - +10 ns
t
CSLOEL
CS LOW to OE LOW time −5 - +5 ns
t
am
memory access time
[2][3]
[4]
(T
cy(CCLK)
× (2 + WST1)) +
(−20)
-- ns
t
am(ibr)
memory access time (initial
burst-ROM)
[2][3]
[4]
(T
cy(CCLK)
× (2 + WST1)) +
(−20)
-- ns
t
am(sbr)
memory access time
(subsequent burst-ROM)
[2][5]
T
cy(CCLK)
+(−20) - - ns
t
h(D)
data hold time
[6]
0--ns
t
CSHOEH
CS HIGH to OE HIGH time −5 - +5 ns
t
OEHANV
OE HIGH to address invalid
time
−5 - +5 ns
t
CHOEL
XCLK HIGH to OE LOW time −5 - +5 ns
t
CHOEH
XCLK HIGH to OE HIGH
time
−5 - +5 ns
Write cycle parameters
t
AVCSL
address valid to CS LOW
time
[1]
T
cy(CCLK)
− 10 - - ns
t
CSLDV
CS LOW to data valid time −5 - +5 ns
t
CSLWEL
CS LOW to WE LOW time −5 - +5 ns
t
CSLBLSL
CS LOW to BLS LOW time −5 - +5 ns
t
WELDV
WE LOW to data valid time −5 - +5 ns
t
CSLDV
CS LOW to data valid time −5 - +5 ns
t
WELWEH
WE LOW to WE HIGH time
[2][4]
T
cy(CCLK)
× (1 + WST2) − 5- T
cy(CCLK)
×
(1 + WST2) + 5
ns
t
BLSLBLSH
BLS LOW to BLS HIGH time
[2][4]
T
cy(CCLK)
× (1 + WST2) − 5- T
cy(CCLK)
×
(1 + WST2) + 5
ns
t
WEHANV
WE HIGH to address invalid
time
[2]
T
cy(CCLK)
− 5-T
cy(CCLK)
+5 ns
t
WEHDNV
WE HIGH to data invalid time
[2]
(2 × T
cy(CCLK)
) − 5 - (2 × T
cy(CCLK)
)+5 ns
t
BLSHANV
BLS HIGH to address invalid
time
[2]
T
cy(CCLK)
− 5-T
cy(CCLK)
+5 ns
LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 39 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
[1] Except on initial access, in which case the address is set up T
cy(CCLK)
earlier.
[2] T
cy(CCLK)
=
1
⁄
CCLK
.
[3] Latest of address valid, CS LOW, OE LOW to data valid.
[4] See the
LPC2210/20 user manual UM10114_1
for a description of the WSTn bits.
[5] Address valid to data valid.
[6] Earliest of CS HIGH, OE HIGH, address change to data invalid.
t
BLSHDNV
BLS HIGH to data invalid
time
[2]
(2 × T
cy(CCLK)
) − 5 - (2 × T
cy(CCLK)
)+5 ns
t
CHDV
XCLK HIGH to data valid
time
- - 10 ns
t
CHWEL
XCLK HIGH to WE LOW time - - 10 ns
t
CHBLSL
XCLK HIGH to BLS LOW
time
- - 10 ns
t
CHWEH
XCLK HIGH to WE HIGH
time
- - 10 ns
t
CHBLSH
XCLK HIGH to BLS HIGH
time
- - 10 ns
t
CHDNV
XCLK HIGH to data invalid
time
- - 10 ns
Table 14. External memory interface dynamic characteristics
…continued
C
L
= 25 pF; T
amb
=40
°
C.
Symbol Parameter Conditions Min Typ Max Unit
Table 15. Standard read access specifications
Access cycle Max frequency WST setting
WST ≥ 0; round up to
integer
Memory access time requirement
standard read
standard write
burst read - initial
burst read - subsequent 3× N/A
f
MAX
2 WST1+
t
RAM
20 ns+
--------------------------------
≤
WST1
t
RAM
20 ns+
t
cy CCLK()
--------------------------------
≥ 2–
t
RAM
t
cy CCLK()
2 WST1+()× 20 ns–≤
f
MAX
1WST2+
t
WRITE
5ns+
----------------------------------
≤
WST2
t
WRITE
t
CYC
5+–
t
cy CCLK()
--------------------------------------------
≥
t
WRITE
t
cy CCLK()
1 WST2+()× 5ns–≤
f
MAX
2 WST1+
t
INIT
20 ns+
--------------------------------
≤
W
ST1
t
INIT
20 ns+
t
cy CCLK()
--------------------------------
≥ 2–
t
INIT
t
cy CCLK()
2 WST1+()× 20 ns–≤
f
MAX
1
t
ROM
20 ns+
---------------------------------
≤
t
ROM
t
cy CCLK()
20 ns–≤
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

LPC2220FET144/G,51

Mfr. #:
Buy LPC2220FET144/G,51
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 64KR/ADC/EX BUS ROMLESS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet