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LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 7 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
L P0.29/
AIN2/
CAP0.3/
MAT0.3
P0.30/
AIN3/
EINT3/
CAP0.0
P1.16/
TRACEP
KT0
P0.0/
TXD0/
PWM1
P3.19/
A19
P0.2/
SCL/
CAP0.0
P3.15/
A15
P0.4/
SCK0/
CAP0.1
P3.12/
A12
V
SS
P1.24/
TRACEC
LK
P0.8/
TXD1/
PWM4
P0.9/
RXD1/
PWM6/
EINT3
M P3.25/
CS2
P3.24/
CS3
V
DD(3V3)
P1.31/
TRST
P3.18/
A18
V
DD(3V3)
P3.16/
A16
P0.3/
SDA/
MAT0.0/
EINT1
P3.13/
A13
P3.9/A9 P0.7/
SSEL0/
PWM2/
EINT2
P3.7/A7 P3.5/A5
NV
DD(1V8)
V
SS
P3.23/
A23/
XCLK
P3.21/
A21
P3.17/
A17
P1.26/
RTCK
V
SS
V
DD(3V3)
P0.5/
MISO0/
MAT0.1
P3.10/
A10
P0.6/
MOSI0/
CAP0.2
P3.8/A8 P3.6/A6
Table 3. Ball allocation
…continued
Row Column
1 2 3 4 5 6 7 8 9 10 11 12 13
LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 8 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
5.2 Pin description
Table 4. Pin description
Symbol Pin (LQFP) Pin (TFBGA) Type Description
P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 0 pins
depends upon the pin function selected via the Pin Connect
Block.
Pins 26 and 31 of port 0 are not available.
P0.0/TXD0/
PWM1
42
[1]
L4
[1]
O TXD0 — Transmitter output for UART0.
O PWM1 — Pulse Width Modulator output 1.
P0.1/RXD0/
PWM3/EINT0
49
[2]
K6
[2]
I RXD0 — Receiver input for UART0.
O PWM3 — Pulse Width Modulator output 3.
I EINT0 — External interrupt 0 input
P0.2/SCL/
CAP0.0
50
[3]
L6
[3]
I/O SCL — I
2
C-bus clock input/output. Open-drain output (for
I
2
C-bus compliance).
I CAP0.0 — Capture input for Timer 0, channel 0.
P0.3/SDA/
MAT0.0/EINT1
58
[3]
M8
[3]
I/O SDA — I
2
C-bus data input/output. Open-drain output (for
I
2
C-bus compliance).
O MAT0.0 — Match output for Timer 0, channel 0.
I EINT1 — External interrupt 1 input.
P0.4/SCK0/
CAP0.1
59
[1]
L8
[1]
I/O SCK0 — Serial clock for SPI0. SPI clock output from master
or input to slave.
I CAP0.1 — Capture input for Timer 0, channel 1.
P0.5/MISO0/
MAT0.1
61
[1]
N9
[1]
I/O MISO0 — Master In Slave OUT for SPI0. Data input to SPI
master or data output from SPI slave.
O MAT0.1 — Match output for Timer 0, channel 1.
P0.6/MOSI0/
CAP0.2
68
[1]
N11
[1]
I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI
master or data input to SPI slave.
I CAP0.2 — Capture input for Timer 0, channel 2.
P0.7/SSEL0/
PWM2/EINT2
69
[2]
M11
[2]
I SSEL0 — Slave Select for SPI0. Selects the SPI interface as
a slave.
O PWM2 — Pulse Width Modulator output 2.
I EINT2 — External interrupt 2 input.
P0.8/TXD1/
PWM4
75
[1]
L12
[1]
O TXD1 — Transmitter output for UART1.
O PWM4 — Pulse Width Modulator output 4.
P0.9/RXD1/
PWM6/EINT3
76
[2]
L13
[2]
I RXD1 — Receiver input for UART1.
O PWM6 — Pulse Width Modulator output 6.
I EINT3 — External interrupt 3 input.
P0.10/RTS1/
CAP1.0
78
[1]
K11
[1]
O RTS1 — Request to Send output for UART1.
I CAP1.0 — Capture input for Timer 1, channel 0.
P0.11/CTS1/
CAP1.1
83
[1]
J12
[1]
I CTS1 — Clear to Send input for UART1.
I CAP1.1 — Capture input for Timer 1, channel 1.
P0.12/DSR1/
MAT1.0
84
[1]
J13
[1]
I DSR1 — Data Set Ready input for UART1.
O MAT1.0 — Match output for Timer 1, channel 0.
LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 9 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
P0.13/DTR1/
MAT1.1
85
[1]
H10
[1]
O DTR1 — Data Terminal Ready output for UART1.
O MAT1.1 — Match output for Timer 1, channel 1.
P0.14/DCD1/
EINT1
92
[2]
G10
[2]
I DCD1 — Data Carrier Detect input for UART1.
I EINT1 — External interrupt 1 input.
Note: LOW on this pin while
RESET is LOW forces on-chip
bootloader to take over control of the part after reset.
P0.15/RI1/
EINT2
99
[2]
E11
[2]
I RI1 — Ring Indicator input for UART1.
I EINT2 — External interrupt 2 input.
P0.16/EINT0/
MAT0.2/CAP0.2
100
[2]
E10
[2]
I EINT0 — External interrupt 0 input.
O MAT0.2 — Match output for Timer 0, channel 2.
I CAP0.2 — Capture input for Timer 0, channel 2.
P0.17/CAP1.2/
SCK1/MAT1.2
101
[1]
D13
[1]
I CAP1.2 — Capture input for Timer 1, channel 2.
I/O SCK1 — Serial Clock for SPI1/SSI/Microwire.
SPI/SSI/Microwire clock output from master or input to slave.
O MAT1.2 — Match output for Timer 1, channel 2.
P0.18/CAP1.3/
MISO1/MAT1.3
121
[1]
D8
[1]
I CAP1.3 — Capture input for Timer 1, channel 3.
I/O MISO1 — Master In Slave Out for SPI1. Data input to SPI
master or data output from SPI slave.
O MAT1.3 — Match output for Timer 1, channel 3.
P0.19/MAT1.2/
MOSI1/CAP1.2
122
[1]
C8
[1]
O MAT1.2 — Match output for Timer 1, channel 2.
I/O MOSI1 — Master Out Slave In for SPI1. Data output from SPI
master or data input to SPI slave.
SPI interface: MOSI line.
SSI: DX/RX line (SPI1 as a master/slave).
Microwire: SO/SI line (SPI1 as a master/slave).
I CAP1.2 — Capture input for Timer 1, channel 2.
P0.20/MAT1.3/
SSEL1/ EINT3
123
[2]
B8
[2]
O MAT1.3 — Match output for Timer 1, channel 3.
I SSEL1 — Slave Select for SPI1/Microwire. Used to select the
SPI or Microwire interface as a slave. Frame synchronization
in case of 4-wire SSI.
I EINT3 — External interrupt 3 input.
P0.21/PWM5/
CAP1.3
4
[1]
C1
[1]
O PWM5 — Pulse Width Modulator output 5.
I CAP1.3 — Capture input for Timer 1, channel 3.
P0.22/CAP0.0/
MAT0.0
5
[1]
D4
[1]
I CAP0.0 — Capture input for Timer 0, channel 0.
O MAT0.0 — Match output for Timer 0, channel 0.
P0.23 6
[1]
D3
[1]
I/O General purpose bidirectional digital port only.
P0.24 8
[1]
D1
[1]
I/O General purpose bidirectional digital port only.
P0.25 21
[1]
H1
[1]
I/O General purpose bidirectional digital port only.
P0.27/AIN0/
CAP0.1/MAT0.1
23
[4]
H3
[4]
I AIN0 — ADC, input 0. This analog input is always connected
to its pin.
I CAP0.1 — Capture input for Timer 0, channel 1.
O MAT0.1 — Match output for Timer 0, channel 1.
Table 4. Pin description
…continued
Symbol Pin (LQFP) Pin (TFBGA) Type Description

LPC2220FET144/G,51

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 64KR/ADC/EX BUS ROMLESS
Lifecycle:
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