LTC3731HUH#TRPBF Datasheet LTC3731HUH#PBF, LTC3731HG#PBF, LTC3731HG#TRPBF | P10-P12

LTC3731H

3731Hfb

operaTion

Main Control Loop

The IC uses a constant frequency, current mode step-down

architecture. During normal operation, each top MOSFET

is turned on each cycle when the oscillator sets the RS

latch, and turned off when the main current comparator,

, resets each RS latch. The peak inductor current at

which I

resets the RS latch is controlled by the voltage

on the I

pin, which is the output of the error amplifier

EA. The EAIN pin receives a portion of output voltage

feedback signal through the external resistive divider and

is compared to the internal reference voltage. When the

load current increases, it causes a slight decrease in the

EAIN pin voltage

relative to the 0.6V reference, which in

turn causes the I

voltage to increase until each inductor’s

average current matches one third of the new load current

(assuming all three current sensing resistors are equal).

In Burst Mode operation and stage shedding mode, after

each top MOSFET has turned off, the bottom MOSFET is

turned on until either the inductor current starts to reverse,

as indicated by current comparator I

, or the beginning

of the next cycle.

The top MOSFET drivers are biased from floating bootstrap

capacitor C

, which is normally recharged through an

external Schottky diode when the top FET is turned off.

When V

decreases to a voltage close to V

OUT

, however,

the loop may enter dropout and attempt to turn on the

top MOSFET continuously. The dropout detector counts

the number of oscillator cycles that the bottom MOSFET

remains off and periodically forces a brief on period to

allow C

to recharge.

The main control loop is shut down by pulling the RUN/SS

pin low. Releasing RUN/SS allows an internal 1.5µA

current source to charge soft-start capacitor C

. When

reaches 1.5V, the main control loop is enabled and

the internally buffered I

voltage is clamped but allowed

to ramp as the voltage on C

continues to ramp. This

“soft-start” clamping prevents abrupt current from being

drawn from the input power source. When the RUN/SS

pin is low, all functions are kept in a controlled state.

The RUN/SS pin is pulled low when the supply input

voltage is below 4V, when the undervoltage lockout pin

(UVADJ) is below 1.2V, or when the IC die temperature

rises above 160°C.

Low Current Operation

The FCB pin is a logic input to select between three modes

of operation.

A) Burst Mode Operation

When the FCB pin voltage is below 0.6V, the controller

performs as a continuous, PWM current mode synchro-

nous switching regulator. The top and bottom MOSFETs

are alternately turned on to maintain the output voltage

independent of direction of inductor current. When the

FCB pin is below V

– 1.5V but greater than 0.6V, the

controller performs as a Burst Mode switching regulator.

Burst Mode operation sets a minimum output current

level before turning off the top switch and turns off the

synchronous MOSFET(s) when the inductor current goes

negative. This combination of requirements will, at low

current, force the I

pin below a voltage threshold that

will temporarily shut off both output MOSFETs until the

output voltage drops slightly. There is a burst compara-

tor having 60mV of hysteresis tied to the I

pin. This

hysteresis results in output signals to the MOSFETs that

turn them on for several cycles, followed by a variable

“sleep” interval depending upon the load current. The

resultant output voltage ripple is held to a very small

value by having the hysteretic comparator after the error

amplifier gain block.

B) Stage Shedding Operation

When the FCB pin is tied to the V

pin, Burst Mode opera-

tion is disabled and the forced minimum inductor current

requirement is removed. This provides constant frequency,

discontinuous current operation over the widest possible

output current range. At approximately 10% of maximum

designed load current, the second and third output stages

are shut off and the phase 1 controller alone is active in

discontinuous current mode. This “stage shedding” opti-

mizes efficiency by eliminating the gate charging losses and

switching losses of the other two output stages. Additional

cycles will be skipped when the output load current drops

below 1% of maximum designed load current in order to

maintain the output voltage. This stage shedding operation

is not as efficient as Burst Mode operation at very light

loads, but does provide lower noise, constant frequency

operating mode down to very light load conditions.

(Refer to Functional Diagram)

LTC3731H

3731Hfb

C) Continuous Current Operation

Tying the FCB pin to ground will force continuous current

operation. This is the least efficient operating mode, but may

be desirable in certain applications. The output can source

or sink current in this mode. When sinking current while

in forced continuous operation, the controller will cause

current to flow back into the input filter capacitor. If large

enough, the input capacitor will prevent the input supply

from boosting to unacceptably high levels; see C

OUT

selection in the Applications Information section.

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be

synchronized to an external source using the PLLIN pin.

The output of the phase detector at the PLLFLTR pin is

also the DC frequency control input of the oscillator, which

operates over a 225kHz to 680kHz range corresponding

to a voltage input from 0V to 2.4V. When locked, the

PLL aligns the turn on of the top MOSFET to the rising

edge of the synchronizing signal. When no frequency

information is supplied to the PLLIN pin, PLLFLTR goes

low, forcing the oscillator to minimum frequency. A DC

source can be applied to the PLLFLTR pin to externally

set the desired operating frequency. A discharge current

of approximately 20µA will be present at the pin with no

PLLIN input signal.

Input capacitance ESR requirements and efficiency losses

are reduced substantially in a multiphase architecture

because the peak current drawn from the input capacitor

is effectively divided by the number of phases used and

power loss is proportional to the RMS current squared. A

3-stage, single output voltage implementation can reduce

input path power loss by 90%.

Power Good

The PGOOD pin is connected to the drain of an internal

N-c

annel MOSFET. The MOSFET is turned on once an

internal delay of about 100µs has elapsed and the output

voltage has been away from its nominal value by greater

than 10%. If the output returns to normal prior to the delay

timeout, the timer is reset. There is no delay time for the

rising of the PGOOD output once the output voltage is

within the ±10% “window.”

Phase Mode

The PHASMD pin determines the phase shift between

the rising edge of the TG1 output and the rising edge of

the CLKOUT signal. Grounding the pin will result in 30

degrees phase shift and tying the pin to V

will result

in 60 degrees. These phase shift values enable extension

to 6- and 12-phase systems. The PGOOD function above

and the PHASMD function are tied to a common pin in

the UH package.

Undervoltage Shutdown Adjust

The voltage applied to the UVADJ pin is compared to the

internal 1.2V reference to have an externally programmable

undervoltage shutdown. The RUN/SS pin is internally held

low until the voltage applied to the UVADJ pin exceeds

the 1.2V threshold.

Short-Circuit Detection

The RUN/SS capacitor is used initially to turn on and limit

the inrush current from the input power source. Once the

controllers have been given time, as determined by the

capacitor on the RUN/SS pin, to charge up the output

capacitors and provide full load current, the RUN/SS

capacitor is then used as a short-circuit timeout circuit.

If the output voltage falls to less than 70% of its nominal

output voltage, the RUN/SS capacitor begins discharg-

ing, assuming that the output is in a severe overcurrent

and/or short-circuit condition. If the condition lasts for

a long enough period, as determined by the size of the

RUN/SS capacitor, the controller will be shut down until the

RUN/SS pin voltage is recycled. This built-in latchoff can

be overridden by providing >5µA at a compliance of 3.8V

to the RUN/SS pin. This additional current shortens the

soft-start period but prevents net discharge of the RUN/SS

capacitor during a severe overcurrent and/or short-circuit

condition. Foldback current limiting is activated when the

output voltage falls below 70% of its nominal level whether

or not the short-circuit latchoff circuit is enabled. Foldback

current limit can be overridden by clamping the EAIN pin

such that the voltage is held above the (70%)(0.6V) or

0.42V level even when the actual output voltage is low. Up

to 100µA of input current can safely be accommodated

by the RUN/SS pin.

operaTion

(Refer to Functional Diagram)

LTC3731H

3731Hfb

operaTion

(Refer to Functional Diagram)

Input Undervoltage Reset

The RUN/SS capacitor will be reset if the input voltage

) is allowed to fall below approximately 4V. The

capacitor on the RUN/SS pin will be discharged until

the short-circuit arming latch is disarmed. The RUN/SS

capacitor will attempt to cycle through a normal soft-start

ramp up after the V

supply rises above 4V. This circuit

prevents power supply latchoff in the event of input power

switching break-before-make situations. The PGOOD pin

is held low during start-up until the RUN/SS capacitor

rises above the short-circuit latchoff arming threshold of

approximately 3.8V.

applicaTions inForMaTion

The basic application circuit is shown in Figure 1 on the

first page of this data sheet. External component selection

is driven by the load requirement, and normally begins

with the selection of an inductance value based upon the

desired operating frequency, inductor current and output

voltage ripple requirements. Once the inductors and op-

erating frequency have been chosen, the current sensing

resistors can be calculated. Next, the power MOSFETs

and Schottky diodes are selected. Finally, C

and C

OUT

are selected according to the voltage ripple require-

ments. The circuit shown in Figure 1 can be configured

for operation up to a MOSFET supply voltage of 28V

(limited by the external MOSFETs and possibly the mini-

mum on-time).

Operating Frequency

The IC uses a constant frequency, phase-lockable ar-

chitecture with the frequency determined by an internal

capacitor. This capacitor is charged by a fixed current plus

an additional current which is proportional to the voltage

applied to the PLLFLTR pin. Refer to the Phase-Locked

Loop and Frequency Synchronization section for additional

information.

A graph for the voltage applied to the PLLFLTR pin versus

frequency is given in Figure 3. As the operating frequency

is increased the gate charge losses will be higher, reducing

efficiency (see Efficiency Considerations). The maximum

switching frequency is approximately 680kHz.

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because

of MOSFET gate charge and transition losses. In addi-

tion to this basic tradeoff, the effect of inductor value on

ripple current and low current operation must also be

considered. The PolyPhase approach reduces both input

and output ripple currents while optimizing individual

output stages to run at a lower fundamental frequency,

enhancing efficiency.

The inductor value has a direct effect on ripple current.

The inductor ripple current ∆I

per individual section,

N, decreases with higher inductance or frequency and

increases with higher V

or V

OUT

∆I

OUT OUT

= −













where f is the individual output stage operating

frequency.

Figure 3. Operating Frequency vs V

PLLFLTR

PLLFLTR PIN VOLTAGE (V)

OPERATING FREQUENCY (kHz)

3731H F03

700

600

500

400

300

200

0.5 1 1.5 2 2.5

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LTC3731HUH#TRPBF

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Description:

Switching Voltage Regulators 3-Phase, 600kHz, Sync Buck Sw Reg Cntr

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