LTC3731H
26
3731Hfb
applicaTions inForMaTion
The worst-case input RMS ripple current for a single stage
design peaks at twice the value of the output voltage. The
worst-case input RMS ripple current for a two stage design
results in peaks at 1/4 and 3/4 of the input voltage, and
the worst-case input RMS ripple current for a three stage
design results in peaks at 1/6, 1/2, and 5/6 of the input
voltage. The peaks, however, are at ever decreasing levels
with the addition of more phases. A higher effective duty
factor results because the duty factors “add” as long as
the currents in each stage are balanced. Refer to AN19
for a detailed description of how to calculate RMS current
for the single stage switching regulator.
Figure 6 illustrates the RMS input current drawn from the
input capacitance versus the duty cycle as determined by
the ratio of input and output voltage. The peak input RMS
current level of the single phase system is reduced by 2/3
in a 3-phase solution due to the current splitting between
the three stages.
The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the V
OUT
/L discharge currents
term from the stages that has their bottom MOSFETs on
subtract current from the (V
CC
– V
OUT
)/L charging current
resulting from the stage which has its top MOSFET on.
The output ripple current for a 3-phase design is:
I
P-P
=
( )( )
( )
>
V
f L
DC V V
OUT
IN OUT
1 3 3–
The ripple frequency is also increased by three, further re-
ducing the required output capacitance when V
CC
< 3V
OUT
as illustrated in Figure 6.
The addition of more phases, by phase locking addi-
tional controllers, always results in no net input or output
ripple at V
OUT
/V
IN
ratios equal to the number of stages
implemented. Designing a system with multiple stages
close to the V
OUT
/V
IN
ratio will significantly reduce the
ripple voltage at the input and outputs and thereby improve
efficiency, physical size and heat generation of the overall
switching power supply. Refer to Application Note 77 for
more information on Polyphase circuits.
Efficiency Calculation
To estimate efficiency, the DC loss terms include the input
and output capacitor ESR, each MOSFET R
DS(ON)
, inductor
resistance R
L
, the sense resistance R
SENSE
and the forward
drop of the Schottky rectifier at the operating output current
and temperature. Typical values for the design example
given previously in this data sheet are:
Main MOSFET R
DS(ON)
= 7mΩ (9mΩ at 90°C)
Sync MOSFET R
DS(ON)
= 7mΩ (9mΩ at 90°C)
C
INESR
= 20mΩ
C
OUTESR
= 3mΩ
R
L
= 2.5mΩ
R
SENSE
= 3mΩ
V
SCHOTTKY
= 0.8V at 15A (0.7V at 90°C)
V
OUT
= 1.3V
V
IN
= 12V
I
MAX
= 45A
d = 0.5%°C (MOSFET temperature coefficient)
N = 3
f = 400kHz
The main MOSFET is on for the duty factor V
OUT
/V
IN
and
the synchronous MOSFET is on for the rest of the period
or simply (1 – V
OUT
/V
IN
). Assuming the ripple current is
small, the AC loss in the inductor can be made small if
a good quality inductor is chosen. The average current,
I
OUT
, is used to simplify the calculations. The equation
below is not exact but should provide a good technique
for the comparison of selected components and give a
result that is within 10% to 20% of the final application.
Determining the MOSFETs’ die temperature may require
iterative calculations if one is not familiar with typical
performance. A maximum operating junction temperature
of 90° to 100°C for the MOSFETs is recommended for
high reliability applications.
Common output path DC loss:
P N
I
N
R R C Lo
COMPATH
MAX
L SENSE OUTESR
≈
+
( )
+
2
sss
This totals 3.7W + C
OUTESR
loss.
