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LTC3731HUH#TRPBF

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LTC3731H
13
3731Hfb
applicaTions inForMaTion
In a PolyPhase converter, the net ripple current seen by
the output capacitor is much smaller than the individual
inductor ripple currents due to the ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.
Figure 4 shows the net ripple current seen by the output
capacitors for the different phase configurations. The
output ripple current is plotted for a fixed output voltage
as the duty factor is varied between 10% and 90% on the
x
-
axis. The output ripple current is normalized against the
inductor ripple current at zero duty factor. The graph can be
used in place of tedious calculations. As shown in Figure
4, the zero output ripple current is obtained when:
V
V
k
N
where k N
OUT
IN
= = 1 2 1, , ..., –
So the number of phases used can be selected to minimize
the output ripple current and therefore the output ripple
voltage at the given input and output voltages. In appli-
cations having a highly varying input voltage, additional
phases will produce the best results.
Accepting larger values of ∆I
L
allows the use of low in-
ductances but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is
∆I
L
= 0.4(I
OUT
)/N, where N is the number of channels and
I
OUT
is the total load current. Remember, the maximum
∆I
L
occurs at the maximum input voltage. The individual
inductor ripple currents are constant determined by the
input and output voltages, and the inductance.
Inductor Core Selection
Once the value for L1 to L3 is determined, the type of induc-
tor must be selected. High efficiency converters generally
cannot afford the core loss found in low cost powdered iron
cores, forcing the use of ferrite, molypermalloy or Kool Mµ
cores. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on inductance
selected. As inductance increases, core losses go down.
Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals cancon-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mµ. Toroids are very space effi-
cient, especially when you can use several layers of wire.
Because they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.
Power MOSFET and D1, D2, D3 Selection
At least two external power MOSFETs must be selected for
each of the three output sections: One N-channel MOSFET
for the top (main) switch and one or more N-channel
MOSFET(s) for the bottom (synchronous) switch. The
number, type and on-resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as
the actual position (main or synchronous) in which the
MOSFET will be used. A much smaller and much lower
input capacitance MOSFET should be used for the top
Figure 4. Normalized Peak Output Current
vs Duty Factor [I
RMS
= 0.3(I
O(P-P)
]
DUTY FACTOR (V
OUT
/V
IN
)
0.1 0.2 0.3 0.4
0.5 0.6 0.7 0.8 0.9
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3731H F04
6-PHASE
12-PHASE
4-PHASE
3-PHASE
2-PHASE
1-PHASE
∆I
O(P-P)
V
O
/fL
LTC3731H
14
3731Hfb
MOSFET in applications that have an output voltage that
is less than 1/3 of the input voltage. In applications where
V
IN
>> V
OUT
, the top MOSFETs’ on-resistance is normally
less important for overall efficiency than its input capaci-
tance at operating frequencies above 300kHz. MOSFET
manufacturers have designed special purpose devices that
provide reasonably low on-resistance with significantly
reduced input capacitance for the main switch application
in switching regulators.
The peak-to-peak MOSFET gate drive levels are set by the
voltage, V
CC
, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BV
DSS
specification for the MOSFETs as well; many of the
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the
on
-
resistance R
DS(ON)
, input capacitance, input voltage
and maximum output current.
MOSFET input capacitance is a combination of sev-
eral components but can be taken from the typical “gate
charge” curve included on most data sheets (Figure 5).
The curve is generated by forcing a constant input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given V
DS
drain
applicaTions inForMaTion
voltage, but can be adjusted for different V
DS
voltages by
multiplying by the ratio of the application V
DS
to the curve
specified V
DS
values. A way to estimate the C
MILLER
term
is to take the change in gate charge from points a and b
on a manufacturers data sheet and divide by the stated
V
DS
voltage specified. C
MILLER
is the most important se-
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. C
RSS
and C
OS
are specified sometimes but
definitions of these parameters are not included.
When the controller is operating in continuous mode
the duty cycles for the top and bottom MOSFETs are
given by:
Main Switch Duty Cycle
V
V
Synchronous SwitchDuty Cycle
V V
V
OUT
IN
IN OUT
IN
=
=
–
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
P
V
V
I
N
R
V
I
N
R C
V V V
f
P
V V
V
I
N
R
MAIN
OUT
IN
MAX
DS ON
IN
MAX
DR MILLER
CC TH IL TH IL
SYNC
IN OUT
IN
MAX
DS ON
=
+
( )
+
( )( )
+
( )
=
+
( )
2
2
2
1
2
1 1
1
d
d
( )
( ) ( )
( )
•
–
–
where N is the number of output stages, d is the tem-
perature dependency of R
DS(ON)
, R
DR
is the effective top
driver resistance (approximately 2Ω at V
GS
= V
MILLER
), V
IN
is the drain potential and the change in drain potential in
the particular application. V
TH(IL)
is the data sheet speci-
fied typical gate threshold voltage specified in the power
MOSFET data sheet at the specified drain current. C
MILLER
is the calculated capacitance using the gate charge curve
from the MOSFET data sheet and the technique described
above.
Figure 5. Gate Charge Characteristic
+
–
V
DS
V
IN
3731H F05
V
GS
MILLER EFFECT
Q
IN
a b
C
MILLER
= (Q
B
– Q
A
)/V
DS
V
GS
V
+
–
LTC3731H
15
3731Hfb
applicaTions inForMaTion
Both MOSFETs have I
2
R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V
IN
< 12V,
the high current efficiency generally improves with larger
MOSFETs, while for V
IN
> 12V, the transition losses rapidly
increase to the point that the use of a higher R
DS(ON)
device
with lower C
MILLER
actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + d ) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs temperature curve, but
d = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The Schottky diodes (D1 to D3 in Figure 1) conduct during
the dead time between the conduction of the two large
power MOSFETs. This prevents the body diode of the bot-
tom MOSFET from turning on, storing charge during the
dead time and requiring a reverse recovery period which
could cost as much as several percent in efficiency. A 2A
to 8A Schottky is generally a good compromise for both
regions of operation due to the relatively small average
current. Larger diodes result in additional transition loss
due to their larger junction capacitance.
C
IN
and C
OUT
Selection
In continuous mode, the source current of each top
N-
channel MOSFET is a square wave of duty cycle V
OUT
/
V
IN
. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a close form
equation can be found in Application Note 77. Figure 6
shows the input capacitor ripple current for different phase
configurations with the output voltage fixed and input volt-
age varied. The input ripple current is normalized against
the DC output current. The graph can be used in place of
tedious calculations. The minimum input ripple current
can be achieved when the product of phase number and
output voltage, N(V
OUT
), is approximately equal to the
input voltage V
IN
or:
V
V
k
N
where k N
OUT
IN
= = 1 2 1, , ..., –
So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages.
In the graph of Figure 4, the local maximum input RMS
capacitor currents are reached when:
V
V
k
N
where k N
OUT
IN
= =
2 1
1 2
–
, , ...,
These worst-case conditions are commonly used for design
because even significant deviations do not offer much relief.
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Always consult the
capacitor manufacturer if there is any question.
The Figure 6 graph shows that the peak RMS input current
is reduced linearly, inversely proportional to the number N
of stages used. It is important to note that the efficiency
loss is proportional to the input RMS current squared and
therefore a 3-stage implementation results in 90% less
power loss when compared to a single phase design. Bat-
tery/input protection fuse resistance (if used), PC board
trace and connector resistance losses are also reduced
by the reduction of the input ripple current in a PolyPhase
system. The required amount of input capacitance is further
DUTY FACTOR (V
OUT
/V
IN
)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0.9
0.6
0.5
0.4
0.3
0.2
0.1
0
3731H F06
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
6-PHASE
4-PHASE
12-PHASE
3-PHASE
2-PHASE
1-PHASE
Figure 6. Normalized Input RMS Ripple Current
vs Duty Factor for One to Six Output Stages
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LTC3731HUH#TRPBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3-Phase, 600kHz, Sync Buck Sw Reg Cntr
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