LTC3731H
23
3731Hfb
applicaTions inForMaTion
The power dissipation on the topside MOSFET can be
estimated. Using a Fairchild FDS6688 for example, R
DS(ON)
= 7mΩ, C
MILLER
= 15nC/15V = 1000pF. At maximum input
voltage with T(estimated) = 50°C:
P
V
V
C C
A
pF
V V V
kHz W
MAIN
≈
( )
+
( )
° − °
( )
[ ]
+
( )
( )( )
Ω
( )( )
+
( )
=
1 8
20
15 1 0 005 50 25
0 007 20
45
2 3
2 1000
1
5 1 8
1
1 8
400 2 2
2
2
.
.
.
– . .
.
Ω
The worst-case power dissipation by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction tem-
perature rise is:
P
V V
V
A W
SYNC
=
−
( ) ( )
Ω
( )
=
20 1 3
20
15 1 25 0 007 1 84
2
.
. . .
A short circuit to ground will result in a folded back
current of:
I
mV
m
ns V
H
A
SC
≈
+
( )
Ω
+
( )
µ
=
25
2 3
1
2
150 20
0 6
7 5
.
.
with a typical value of R
DS(ON)
and d = (0.005/°C)(50°C)
= 0.25. The resulting power dissipated in the bottom
MOSFET is:
P
SYNC
= (7.5A)
2
(1.25)(0.007Ω) ≈ 0.5W
which is less than one third of the normal, full load con-
ditions. Incidentally, since the load no longer dissipates
any power, total system power is decreased by over 90%.
Therefore, the system actually cools significantly during
a shorted condition!
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 11. Check the following in the
PC layout:
1) Are the signal and power ground paths isolated? Keep
the SGND at one end of a printed circuit path thus prevent-
ing MOSFET currents from traveling under the IC. The IC
signal ground pin should be used to hook up all control
circuitry on one side of the IC, routing the copper through
SGND, under the IC covering the “shadow” of the package,
connecting to the PGND pin and then continuing on to the
(–) plates of C
IN
and C
OUT
. The V
CC
decoupling capacitor
should be placed immediately adjacent to the IC between
the V
CC
pin and PGND. A 1µF ceramic capacitor of the X7R
or X5R type is small enough to fit very close to the IC to
minimize the ill effects of the large current pulses drawn
to drive the bottom MOSFETs. An additional 5µF to 10µF
of ceramic, tantalum or other very low ESR capacitance is
recommended in order to keep the internal IC supply quiet.
The power ground returns to the sources of the bottom
N
-channel MOSFETs, anodes of the Schottky diodes and
(–) plates of C
IN
, which should have as short lead lengths
as possible.
2) Does the V
FB
pin connect directly to the feedback re-
sistors? The resistive divider R1/R2 must be connected
between the (+) plate of C
OUT
and signal ground.
3) Are the SENSE
–
and SENSE
+
printed circuit traces for
each channel routed together with minimum PC trace spac-
ing? The filter capacitors between SENSE
+
and SENSE
–
for
each channel should be as close as possible to the pins of
the IC. Connect the SENSE
–
and SENSE
+
pins to the pads
of the sense resistor as illustrated in Figure 12.
4) Do the (+) plates of C
PWR
connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the pulsed current to the MOSFETs.
5) Keep the switching nodes, SWITCH, BOOST and TG
away from sensitive small-signal nodes (SENSE
+
, SENSE
–
,
EAIN). Ideally the SWITCH, BOOST and TG printed circuit
traces should be routed away and separated from the IC
and especially the “quiet” side of the IC. Separate the high
dv/dt traces from sensitive small-signal nodes with ground
traces or ground planes.
6) Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.
