LTC3731H
8
3731Hfb
pin FuncTions
BG1 to BG3: High Current Gate Drives for Bottom N-Channel
MOSFETs. Voltage swing at these pins is from ground to
V
CC
.
BOOST1 to BOOST3: Positive Supply Pins to the Topside
Floating Drivers. Bootstrapped capacitors, charged with
external Schottky diodes and a boost voltage source, are
connected between the BOOST and SW pins. Voltage swing
at the BOOST pins is from boost source voltage (typically
V
CC
) to this boost source voltage + V
IN
(where V
IN
is the
external MOSFET supply rail).
CLKOUT: Output clock signal available to synchronize other
controller ICs for additional MOSFET stages/phases.
EAIN: This is the input to the error amplifier that com-
pares the feedback voltage to the internal 0.6V reference
voltage.
FCB: Forced Continuous Control Input. The voltage ap-
plied to this pin sets the operating mode of the controller.
The forced continuous current mode is active when the
applied voltage is less than 0.6V. Burst Mode operation
will be active when the pin is allowed to float and a stage
shedding mode will be active if the pin is tied to the V
CC
pin. (Do not apply voltage directly to this pin prior to the
application of voltage on the V
CC
pin.)
PGOOD: This open-drain output is pulled low when the
output voltage has been outside the PGOOD tolerance
window for the V
PGDLY
delay of approximately 100µs.
I
TH
: Error Amplifier Output and Switching Regulator Com-
pensation Point. All three current comparator’s thresholds
increase with this control voltage.
PGND: Driver Power Ground. This pin connects directly
to the sources of the bottom N-channel external MOSFETs
and the (–) terminals of C
IN
.
PHASMD: This pin determines the phase shift between
the first controller’s rising TG signal and the rising edge
of the CLKOUT signal. Logic 0 yields 30 degrees and logic
1 yields 60 degrees.
PLLIN: Synchronization Input to Phase Detector. This
pin is internally terminated to SGND with 50kΩ. The
phase-locked loop will force the rising top gate signal of
controller 1 to be synchronized with the rising edge of
the PLLIN signal.
PLLFLTR: The phase-locked loop’s lowpass filter is tied
to this pin. Alternatively, this pin can be driven with an AC
or DC voltage source to vary the frequency of the internal
oscillator. (Do not apply voltage directly to this pin prior
to the application of voltage on the V
CC
pin.)
RUN/SS: Combination of Soft-Start, Run Control Input
and Short-Circuit Detection Timer. A capacitor to ground
at this pin sets the ramp time to full current output as well
as the time delay prior to an output voltage short-circuit
shutdown. A minimum value of 0.01µF is recommended
on this pin.
SENSE1
+
, SENSE2
+
, SENSE3
+
, SENSE1
–
, SENSE2
–
,
SENSE3
–
: The Inputs to Each Differential Current Com-
parator. The I
TH
pin voltage and built-in offsets between
SENSE
–
and SENSE
+
pins, in conjunction with R
SENSE
, set
the current trip threshold level.
SGND: Signal Ground. This pin must be routed sepa-
rately under the IC to the PGND pin and then to the main
ground plane. The exposed pad in the UH package must
be soldered to PCB ground for electrical contact and rated
thermal performance.
SW1 to SW3: Switch Node Connections to Inductors.
Voltage swing at these pins is from a Schottky diode
(external) voltage drop below ground to V
IN
(where V
IN
is the external MOSFET supply rail).
TG1 to TG3: High Current Gate Drives for Top N-channel
MOSFETs. These are the outputs of floating drivers with
a voltage swing equal to the boost voltage source super-
imposed on the switch node voltage SW.
UVADJ: Input to the Undervoltage Shutdown Compara-
tor. When the applied input voltage is less than 1.2V, this
comparator turns off the output MOSFET driver stages
and discharges the RUN/SS capacitor.
V
CC
: Main Supply Pin. Because this pin supplies both the
controller circuit power as well as the high power pulses
supplied to drive the external MOSFET gates, this pin
needs to be very carefully and closely decoupled to the
IC’s PGND pin.
VDR: Supplies power to the bottom gate drivers only. This
pin needs to be very carefully and closely decoupled to
the IC’s PGND pin.
