This is information on a product in full production.
September 2012 Doc ID 17526 Rev 2 1/26
26
ST7570
S-FSK power line networking system-on-chip
Datasheet — production data
Features
Fully integrated narrow-band power line
networking system-on-chip
High performing PHY processor with
embedded turn-key firmware for spread
frequency shift keying (S-FSK) modulation:
Programmable bit rate up to 2.4 Kbps (@
50 Hz)
1 Hz step programmable carriers up to
148.5 kHz
Signal to noise ratio estimation
Received signal strength indication
Protocol engine embedding:
IEC61334-5-1 PHY and MAC layers
Alarm management
Repeater Call procedure
Intelligent search initiator process
On chip peripherals:
Host controller UART interface
Fully integrated analog front end:
ADC and DAC
PGA with automatic gain control for high
receiving sensitivity
High linearity modulated signal generation
Fully integrated single-ended power amplifier
for line driving
Up to 1 A rms, 14 V p-p output
Configurable Active filtering topology
Very high linearity
Embedded temperature sensor
Current control feature
8 to 18 V power amplifier supply
3.3 V or 5 V digital I/O supply
Integrated 5 V and 1.8 V linear regulators for
AFE and digital core supply
Mains zero crossing synchronization
Suitable for EN50065 and FCC part 15
compliant applications
VFQFPN48 package with exposed pad
-40 °C to +85 °C temperature range
Applications
Smart metering applications
Street lighting control
Command and control networking
Description
The ST7570 is a powerful power line networking
system-on-chip. It combines a high-performance
PHY processor core and a protocol controller core
with a fully integrated analog front end (AFE) and
line driver.
The ST7570 features allow the most cost-
effective, single-chip power line communication
solution based on IEC61334-5-1 S-FSK standard.
Table 1. Device summary
Order codes Package Packaging
ST7570
VFQFPN48
Tube
ST7570TR Tape and reel
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www.st.com
Contents ST7570
2/26 Doc ID 17526 Rev 2
Contents
1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Analog front end (AFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Reception path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Transmission path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Current and voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5 Thermal shutdown and temperature control . . . . . . . . . . . . . . . . . . . . . . . 16
5.6 Zero-crossing PLL and delay compensation . . . . . . . . . . . . . . . . . . . . . . 16
6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9 Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1 S-FSK principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.2 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.3 Frame structure at physical level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.4 Frame timing and time-slot synchronization . . . . . . . . . . . . . . . . . . . . . . . 22
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ST7570 Device overview
Doc ID 17526 Rev 2 3/26
1 Device overview
Realized using a multi-power technology with state-of-the-art VLSI CMOS lithography, the
ST7570 is based on dual digital core architecture (a PHY processor engine and a protocol
controller core) to guarantee outstanding communication performance with a high level of
flexibility and programmability.
The on-chip analog front end, featuring analog to digital and digital to analog conversion and
automatic receiver gain control, plus the integrated Power Amplifier delivering up to 1Arms
output current, makes the ST7570 the first complete system-on-chip for power line
communication.
Line coupling network design is also simplified, leading to a very low cost BOM. Safe and
performing operations are guaranteed while keeping power consumption and distortion
levels very low, thus making ST7570 an ideal platform for the most stringent application
requirements and regulatory standards compliance.
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ST7570TR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Network Controller & Processor ICs S-FSK Power Line SOC PHY 2.4 kpbs
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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