ST7570 Analog front end (AFE)
Doc ID 17526 Rev 2 13/26
5 Analog front end (AFE)
5.1 Reception path
Figure 4 shows the block diagram of the ST7570 input receiving path. The main blocks are a
wide input range analog programmable gain amplifier (PGA) and the analog to digital
converter (ADC).
Figure 5. reception path block diagram
The PGA is controlled by an embedded loop algorithm, adapting the PGA gain to amplify or
attenuate the input signal according to the input voltage range for the ADC.
The PGA gain ranges from -18 dB up to 30 dB, with steps of 6 dB (typ.), as described in
Tabl e 5 .
5.2 Transmission path
Figure 5 shows the transmission path block diagram. it is mainly based on a digital to analog
converter (DAC), capable to generate a linear signal up to its full scale output. A gain control
block before the DAC gives the possibility to scale down the output signal to match the
desired transmission level.
Table 6. PGA gain table
PGA code PGA gain (typ) [dB] RX_IN max range [V p-p]
0-1816
1-128
2-64
302
461
5 12 0.500
6 18 0.250
7 24 0.125
8 30 0.0625
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Analog front end (AFE) ST7570
14/26 Doc ID 17526 Rev 2
Figure 6. Transmission path block diagram
The amplitude of the transmitted signal can be set on a 32-step logarithmic scale through
the TX_GAIN parameter, introducing an attenuation ranging from 0 dB (typ.), corresponding
to the TX_OUT full range, down to -31 dB (typ.).
The attenuation set by the TX_GAIN parameter can be calculated using the formula of
Equation 1:
Equation 1 Output attenuation A [dB] vs. TX GAIN
5.3 Power amplifier
The integrated power amplifier is characterized by very high linearity, required to be
compliant with the different international regulations (CENELEC, FCC etc.) limiting the
spurious conducted emissions on the mains, and a current capability of 1 A rms that allows
the amplifier driving even very low impedance points of the network.
All the pins of the power amplifier are accessible, making it possible to build an active filter
network to increase the linearity of the output signal.
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ST7570 Analog front end (AFE)
Doc ID 17526 Rev 2 15/26
5.4 Current and voltage control
The power amplifier output current sensing is performed by mirroring a fraction of the output
current and making it flow through a resistor R
CL
connected between the C
L
pin and VSS.
The following relationship can be established between V(CL) and I(PA_OUT):
Equation 2 V(CL) vs. I(PA_OUT)
The voltage level V(CL) is compared with the internal threshold CL_TH. When the V(CL)
exceeds the CL_TH level, the V(TX_OUT) voltage is decreased by one TX_GAIN step at a
time until V(CL) goes below the CL_TH threshold.
The current sense circuit is depicted in Figure 6.
Figure 7. PA_OUT current sense circuit
The R
CL
value to get the desired output current limit I(PA_OUT)LIM can be calculated
according to Equation 3:
Equation 3 R
CL
calculation
Note that I(PA_OUT)
LIM
is expressed as peak current, so the corresponding rms current
value shall be calculated according to the transmitted signal waveform.
The R
CL
value to get 1 A rms output current limit, calculated with typical values for CL_TH
and CL_RATIO parameters, is indicated in Ta ble 7.
Table 7. CL resistor typical values
Parameter Description Value Unit
R
CL
Resistor value for I(PA_OUT) MAX = 1 A rms (1.41 A peak) 133 Ω
VCL()
R
CL
I PA_OUT()
CL_RATIO
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ST7570TR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Network Controller & Processor ICs S-FSK Power Line SOC PHY 2.4 kpbs
Lifecycle:
New from this manufacturer.
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