MAX8819CETI+ Datasheet MAX8819BETI+, MAX8819AETI+, MAX8819CETI+ | P19-P21

MAX8819A/MAX8819B/MAX8819C

PMIC with Integrated Chargers and Smart

Power Selector in a 4mm x 4mm TQFN

______________________________________________________________________________________ 19

• The battery charger is enabled by the processor dri-

ving the CEN input high. A valid input must be avail-

able at DC. The battery charger is disabled without

a valid input at DC or by driving CEN low.

• The system current has priority over the battery

charger; the battery charger automatically reduces

its charge current to maintain the input current limit

while still providing the system current (I

SYS

• The input current limit is tapered down from full cur-

rent to zero current when the die temperature transi-

tions from +100°C to +120°C. Since I

SYS

has priority

over the battery charge current, the battery charge

current tapers down before I

SYS

. The overall result is

self-regulation of die temperature (see the

Thermal

Limiting and Overload Protection

section for more

information).

• The battery charger stops charging in done mode

as shown in Figures 2 and 3.

Charge Status Output (CHG)

CHG is an open-drain, active-low output that indicates

charger status. As shown in Figures 2 and 3, CHG is

low when the charger is in its prequalification or fast-

charge states. When a timer count is exceeded in

either state, CHG indicates the fault by blinking at a

2Hz rate and remains in that state until the charger is

reset by CEN going low, removal of DC or setting

DLIM[1:2] = 11.

When the MAX8819_ is used with a microprocessor

(μP), connect a pullup resistor between CHG and the

system logic voltage to indicate charge status to the

μP. Alternatively, CHG sinks up to 20mA for an LED

charge indicator.

If the charge status output feature is not required, con-

nect CHG to ground or leave unconnected.

Charge Timer

As shown in Figure 3, a fault timer prevents the battery

from charging indefinitely. In prequalification mode, the

charge time is internally fixed to 33min.

PREQUAL

= 33min

In fast-charge mode, the charge timer is internally fixed

to 660min.

FSTCHG

= 660min

When the charger exits fast-charge mode, a fixed

33min top-off mode is entered:

TOPOFF

= 33min

While in the constant-current fast-charge mode (Figure

2), if the MAX8819_ reduces the battery charge current

due to its internal die temperature or large system loads,

it slows down the charge timer. This feature eliminates

nuisance charge timer faults. When the battery charge

current is between 100% and 50% of its programmed

fast-charge level, the fast-charge timer runs at full

speed. When the battery charge current is between

50% and 20% programmed fast-charge level, the fast-

charge timer is slowed by 2x. Similarly, when the bat-

tery charge current is below 20% of the programmed

fast-charge level, the fast-charge timer is paused. The

fast-charge timer is not slowed or paused when the

charger is in the constant voltage portion of its fast-

charge mode (Figure 2) where the charge current

reduces normally.

FAST-CHARGE, PREQUALIFICATION, AND TOP-OFF

CURRENT vs. CHARGE-SETTING RESISTOR

CISET

(kΩ)

CURRENT (mA)

0 5 10 15 20

100

1000

10,000

PREQUAL,

TOPOFF

CHGMAX

Figure 4. Calculated Charge Currents vs. R

CISET

(kΩ)

CHGMAX

(mA)

PREQUAL

(mA)

TOPOFF

(mA)

3.01 1000 100 100

4.02 746 75 75

4.99 601 60 60

6.04 497 50 50

6.98 430 43 43

8.06 372 37 37

9.09 330 33 33

10 300 30 30

11 273 27 27

12.1 248 25 25

13 231 23 23

14 214 21 21

15 200 20 20

Table 2. Calculated Charge Currents vs.

CISET

MAX8819A/MAX8819B/MAX8819C

PMIC with Integrated Chargers and Smart

Power Selector in a 4mm x 4mm TQFN

20 ______________________________________________________________________________________

Charge Current (CISET)

As shown in Table 2 and Figure 4, a resistor from CISET

to ground (R

CISET

) sets the maximum fast-charge cur-

rent (I

CHGMAX

), the charge current in prequalification

mode (I

PREQUAL

), and the top-off threshold (I

TOPOFF

The MAX8819_ supports values of I

CHGMAX

from 200mA

to 1000mA. Select the R

CISET

as follows:

Determine I

CHGMAX

by considering the characteristics

of the battery. It is not necessary to limit the charge cur-

rent based on the capabilities of the expected AC-to-

DC adapter or USB/DC input current limit, the system

load, or thermal limitations of the PCB. The IC automati-

cally lowers the charging current as necessary to

accommodate for these factors.

For the selected value of R

CISET

, calculate I

CHGMAX

PREQUAL

, and I

TOPOFF

as follows:

Step-Down Converters

(REG1, REG2, REG3)

REG1, REG2, and REG3 are high-efficiency, 2MHz cur-

rent-mode step-down converters with adjustable outputs.

REG1 is designed to deliver 400mA for the MAX8819A/

MAX8819B and 550mA for the MAX8819C. REG2 and

REG3 are designed to deliver 300mA for the MAX8819A/

MAX8819B and 500mA for the MAX8819C.

The PV13 step-down regulator power input must be

connected to SYS. PV2 must also be connected to SYS

for normal operation of REG2, but REG2 can be dis-

abled by connecting PV2, FB2, and PG2 to GND. When

REG2 is disabled, LX2 can be unconencted or con-

nected to GND. The step-down regulators operate with

SYS

from 2.6V to 5.5V. Undervoltage lockout ensures

that the step-down regulators do not operate with SYS

below 2.55V (max).

See the

Step-Down Converter Enable/Disable (EN123)

and Sequencing

section for how to enable and disable

the step-down converters. When enabled, the

MAX8819_ gradually ramps each output up during a

2.6ms soft-start time. When enabled, the MAX8819C

sequentially ramps up each output. Soft-start eliminates

input current surges when regulators are enabled.

See the

Step-Down Control Scheme

section for informa-

tion about the step-down converters control scheme.

The IC uses external resistor-dividers to set the step-

down output voltages between 1V and V

SYS

. Use at

least 10μA of bias current in these dividers to ensure no

change in the stability of the closed-loop system. To set

the output voltage, select a value for the resistor con-

nected between FB_ and GND (R

FBL

). The recom-

mended value is 100kΩ. Next, calculate the value of the

resistor connected from FB_ to the output (R

FBH

REG1, REG2, and REG3 are optimized for high, medi-

um, and low output voltages, respectively. The highest

overall efficiency occurs with V1 set to the highest out-

put voltage and V3 set to the lowest output voltage.

Step-Down Control Scheme

At light load, the step-down converter switches only as

needed to supply the load. This improves light-load effi-

ciency. At higher load currents (~80mA), the step-down

converter transitions to fixed 2MHz switching.

Step-Down Dropout and Minimum Duty Cycle

All of the step-down regulators are capable of operat-

ing in 100% duty-cycle dropout, however, REG1 has

been optimized for this mode of operation. During

100% duty-cycle operation, the high-side p-channel

MOSFET turns on constantly, connecting the input to

the output through the inductor. The dropout voltage

) is calculated as follows:

where:

= p-channel power switch R

DS(ON)

LSR

= external inductor ESR

The minimum duty cycle for all step-down regulators is

12.5% (typ), allowing a regulation voltage as low as 1V

over the full SYS operating range. REG3 is optimized

for low duty-cycle operation.

Step-Down Input Capacitor

The input capacitor in a step-down converter reduces

current peaks drawn from the power source and

reduces switching noise in the controller. The imped-

ance of the input capacitor at the switching frequency

must be less than that of the source impedance of the

supply so that high-frequency switching currents do not

pass through the input source.

VI RR

DO LOAD P LSR

()

FBH FBL

OUT

=× −

⎛

⎝

⎜

⎞

⎠

⎟

II xI

CHGMAX

CISET

PREQUAL TOPOFF CHGMAX

2000

CISET

CHGMAX

=×2000

15.

MAX8819A/MAX8819B/MAX8819C

PMIC with Integrated Chargers and Smart

Power Selector in a 4mm x 4mm TQFN

______________________________________________________________________________________ 21

The step-down regulator power inputs are critical dis-

continuous current paths that require careful bypass-

ing. In the PCB layout, place the step-down converter

input bypass capacitors as close as possible to each

pair of switching converter power input pins (PV_ to

PG_) to minimize parasitic inductance. If making con-

nections to these capacitors through vias, be sure to

use multiple vias to ensure that the layout does not

insert excess inductance or resistance between the

bypass capacitor and the power pins.

The input capacitor must meet the input ripple current

requirement imposed by the step-down converter.

Ceramic capacitors are preferred due to their low ESR

and resilience to power-up surge currents. Choose the

input capacitor so that its temperature rise due to input

ripple-current does not exceed approximately +10°C.

For a step-down DC-DC converter, the maximum input

ripple current is half of the output current. This maxi-

mum input ripple current occurs when the step-down

converter operates at 50% duty factor (V

= 2 x V

OUT

Bypass PV13 to PG1 and PG3 with a 4.7μF ceramic

capacitor. If REG2 is required, bypass PV2 to PG2 with

a 2.2μF capacitor. Use capacitors that maintain their

capacitance over temperature and DC bias. Ceramic

capacitors with an X7R or X5R temperature characteris-

tic generally perform well. The capacitor voltage rating

should be 6.3V or greater.

Step-Down Output Capacitors

The output capacitance keeps output ripple small and

ensures control-loop stability. The output capacitor must

have low impedance at the switching frequency.

Ceramic, polymer, and tantalum capacitors are suitable

with ceramic exhibiting the lowest ESR and lowest high-

frequency impedance. The MAX8819A/MAX8819B

require at least 10μF of output capacitance. The

MAX8819C requires ar least 22μF of output capacitance.

As the case sizes of ceramic surface-mount capacitors

decreases, their capacitance vs. DC bias voltage char-

acteristic becomes poor. Due to this characteristic, it is

possible for 0805 capacitors to perform well while 0603

capacitors of the same value may not. The MAX8819A/

MAX8819B require a nominal output capacitance of

10μF, however, after their DC bias voltage derating, the

output capacitance must be at least 7.5μF.

Step-Down Inductor

Choose the step-down converter inductance to be

4.7μH. The minimum recommended saturation current

requirement is 700mA. In PWM mode, the peak induc-

tor currents are equal to the load current plus one half

of the inductor ripple current. See Table 3 for suggested

inductors.

MANUFACTURER SERIES

INDUCTANCE

(µH)

ESR

(mΩ)

CURRENT RATING

(mA)

DIMENSIONS

(mm)

CDRH2D11HP 4.7 190 750 3.0 x 3.0 x 1.2 = (10.8mm)

Sumida

CDH2D09 4.7 218 700 3.0 x 3.0 x 1.0= (9.0mm)

NR3012 4.7 130 770 3.0 x 3.0 x 1.2 = (10.8mm)

Taiyo Yuden

NR3010 4.7 190 750 3.0 x 3.0 x 1.0 = (9.0mm)

VLF3012 4.7 160 740 2.8 x 2.6 x 1.2 = (8.7mm)

TDK

VLF3010 4.7 240 700 2.8 x 2.6 x 1.0 = (7.3mm)

TOKO DE2812C 4.7 130 880 3.0 x 2.8 x 1.2 = (10.8mm)

MIPF2520 4.7 110 1100 2.5 x 2.0 x 1.0 = (5mm)

FDK

MIPF2016 4.7 160 900 2.0 x 1.6 x 1.0 = (3.2mm)

Table 3. Suggested Inductors

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

MAX8819CETI+

Mfr. #:

Buy MAX8819CETI+

Manufacturer:

Maxim Integrated

Description:

Power Management Specialized - PMIC PMIC w/Charger & Smart Power Selector

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX8819CETI+

MAX8819CETI+

Products related to this Datasheet