CS61574A-IL1Z Datasheet CS61574A-IL1Z, CS61574A-IL1ZR, CS61575-IL1Z | P13-P15

A block diagram of the receiver is shown in Fig-

ure 10. The two leads of the transformer (RTIP

and RRING) have opposite polarity allowing the

receiver to treat RTIP and RRING as unipolar sig-

nals. Comparators are used to detect pulses on

RTIP and RRING. The comparator thresholds are

dynamically established at a percent of the peak

level (50% of peak for E1, 65% of peak for T1;

with the slicing level selected by LEN2/1/0 in-

puts).

The leading edge of an incoming data pulse trig-

gers the clock phase selector. The phase selector

chooses one of the 13 available phases which the

delay line produces for each bit period. The out-

put from the phase selector feeds the clock and

data recovery circuits which generate the recov-

ered clock and sample the incoming signal at

appropriate intervals to recover the data.

Data sampling will continue at the periods se-

lected by the phase selector until an incoming

pulse deviates enough to cause a new phase to be

selected for data sampling. The phases of the de-

lay line are selected and updated to allow as much

as 0.4 UI of jitter from 10 kHz to 100 kHz, with-

out error. The jitter tolerance of the receiver

exceeds that shown in Figure 11. Additionally,

this method of clock and data recovery is tolerant

of long strings of consecutive zeros. The data

sampler will continuously sample data based on

its last input until a new pulse arrives to update

the clock phase selector.

The delay line is continuously calibrated using

the crystal oscillator reference clock. The delay

line produces 13 phases for each cycle of the ref-

erence clock. In effect, the 13 phases are

analogous to a 20 MHz clock when the reference

clock is 1.544 MHz. This implementation utilizes

the benefits of a 20 MHz clock for clock recovery

without actually having the clock present to im-

pede analog circuit performance.

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Figure 10. Receiver Block Diagram

CS61574A CS61575

DS154F3 13

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In the Hardware Mode, data at RPOS and RNEG

should be sampled on the rising edge of RCLK,

the recovered clock. In the Extended Hardware

Mode, data at RDATA should be sampled on the

falling edge of RCLK. In the Host Mode, CLKE

determines the clock polarity for which output

data should be sampled as shown in Table 5.

Loss of Signal

The receiver will indicate loss of signal after

power-up, reset or upon receiving 175 consecu-

tive zeros. A digital counter counts received

zeros, based on RCLK cycles. A zero is received

when the RTIP and RRING inputs are below the

input comparator slicing threshold level estab-

lished by the peak detector. After the signal is

removed for a period of time the data slicing

threshold level decays to approximately

300 mV

peak

If ACLKI is present during the LOS state, ACLKI

is switched into the input of the jitter attenuator,

resulting in RCLK matching the frequency of

ACLKI. The jitter attenuator buffers any instanta-

neous changes in phase between the last

recovered clock and the ACLKI reference clock.

This means that RCLK will smoothly transition

to the new frequency. If ACLKI is not present,

then the crystal oscillator of the jitter attenuator is

forced to its center frequency. Table 6 shows the

status of RCLK upon LOS.

Jitter Attenuator

The jitter attenuator reduces wander and jitter in

the recovered clock signal. It consists of a 32 or

192-bit FIFO, a crystal oscillator, a set of load

capacitors for the crystal, and control logic. The

jitter attenuator exceeds the jitter attenuation re-

quirements of Publications 43802 and REC.

G.742. A typical jitter attenuation curve is shown

in Figure 12. The CS61575 fully meets AT&T

62411 jitter attenuation requirements. The

CS61574A will have a discontinuity in the jitter

transfer function when the incoming jitter ampli-

tude exceeds approximately 23 UIs.

The jitter attenuator works in the following man-

ner. The recovered clock and data are input to the

FIFO with the recovered clock controlling the

FIFO’s write pointer. The crystal oscillator con-

trols the FIFO’s read pointer which reads data out

of the FIFO and presents it at RPOS and RNEG

(or RDATA). RCLK is equivalent to the oscilla-

tor’s output. By changing the load capacitance

that the IC presents to the crystal, the oscillatior

frequency (and RCLK) is adjusted to the average

frequency of the recovered signal. Logic deter-

mines the phase relationship between the read and

write pointers and decides how to adjust the load

capacitance of the crystal. Jitter is absorbed in the

FIFO according to the jitter transfer characteristic

shown in Figure 12.

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Table 5. Data Output/Clock Relationship

CS61574A CS61575

14 DS154F3

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The FIFO in the jitter attenuator is designed to

prevent overflow and underflow. If the jitter am-

plitude becomes very large, the read and write

pointers may get very close together. Should they

attempt to cross, the oscillator’s divide by four

circuit adjusts by performing a divide by 3 1/2 or

divide by 4 1/2 to prevent the overflow or under-

flow. During this activity, data will never be lost.

The difference between the CS61575 and

CS61574A is the depth of the FIFO in the jitter

attenuator. The CS61575 has a 192-bit FIFO

which allows it to attenuate large amplitude, low

frequency jitter as required by AT&T 62411 (e.g.,

28 UIpp @ 300 Hz). This makes the CS61575

ideal for use in T1 Customer Premises Equipment

which must be compatible with AT&T 62411 re-

quirements. In single-line Stratum 4, Type II

systems which are loop-timed, he CS61575 re-

covered clock can be used as the transmit clock

eliminating the need for an external system clock

synchronizer. In Stratum 4, Type I systems which

transfer timing and require a clock synchronizer,

the CS61575 simplifies the design of the synchro-

nizer by absorbing large amplitude low frequency

jitter before it reaches the synchronizer.

The CS61574A has a 32-bit FIFO which allows it

to absorb jitter with minimum data delay in T1

and E1 switching or transmission applications.

The CS61574A will tolerate large amplitude jitter

by tracking rather than attenuating it, preventing

data errors so that the jitter may be absorbed in

external frame buffers. With large amplitude input

jitter, the CS61574A jitter transfer function may

exhibit some jitter peaking, but will offer per-

formance comparable to the CS61574.

The jitter attenuator may be bypassed by pulling

XTALIN to RV+ through a 1 kΩ resistor and pro-

viding a 1.544 MHz (or 2.048 MHz) clock on

ACLKI. RCLK may exhibit quantization jitter of

approximately 1/13 UIpp and a duty cycle of ap-

proximately 30% (70%) when the attenuator is

disabled.

Local Loopback

Local loopback is selected by taking LLOOP, pin

27, high or by setting the LLOOP register bit via

the serial interface.

The local loopback mode takes clock and data

presented on TCLK, TPOS, and TNEG (or

TDATA), sends it through the jitter attenuator and

outputs it at RCLK, RPOS and RNEG (or

RDATA). If the jitter attenuator is disabled, it is

bypassed. Inputs to the transmitter are still trans-

mitted on TTIP and TRING, unless TAOS has

been selected in which case, AMI-coded continu-

ous ones are transmitted at the TCLK frequency.

The receiver RTIP and RRING inputs are ignored

when local loopback is in effect.

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Figure 12. Typical Jitter Transfer Function

CS61574A CS61575

DS154F3 15

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P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P34

CS61574A-IL1Z

Mfr. #:

Buy CS61574A-IL1Z

Manufacturer:

Cirrus Logic

Description:

Telecom Interface ICs IC T1/E1 Ln Intrfc UnitF/Stratum-4 apps

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CS61574A-IL1Z

CS61574A-IL1Z

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