THEORY OF OPERATION
Enhancements in CS61575 and CS61574A
The CS61574A and CS61575 provide higher per-
formance and more features than the CS61574
including:
• AT&T 62411, Stratum 4 compliant jitter at-
tenuation over the full range of operating
frequency and jitter amplitude (CS61575),
• 50% lower power consumption,
• Internally matched transmitter output im-
pedance for improved signal quality,
• Optional AMI, B8ZS, HDB3 encoder/de-
coder or external line coding support,
• Receiver AIS (unframed all ones) detection,
• ANSI T1.231-1993 compliant receiver
LOS (Loss of Signal) handling,
• Transmitter TTIP and TRING outputs are
forced low when TCLK is static,
• The Driver Performance Monitor operates
over a wider range of input signal levels.
Existing designs using the CS61574 can be con-
verted to the higher performance, pin-compatible
CS61574A or CS61575 if the transmit trans-
former is replaced by a pin-compatible
transformer with a new turns ratio.
Understanding the Difference Between the
CS61575 and CS61574A
The CS61574A and CS61575 provide receiver
jitter attenuation performance optimized for dif-
ferent applications. The CS61575 is optimized to
attenuate large amplitude, low frequency jitter for
T1 Customer Premises Equipment (CPE) applica-
tions as required by AT&T 62411. The
CS61574A is optimized to minimize data delay in
T1 and E1 switching or transmission applications.
Refer to the "Jitter Attenuator" section for addi-
tional information.
Introduction to Operating Modes
The CS61574A and CS61575 support three oper-
ating modes which are selected by the level of the
MODE pin as shown in Tables 1 and 2, Figure 7,
and Figures A1-A3 of the Applications section.
The modes are Hardware Mode, Extended Hard-
ware Mode, and Host Mode. In Hardware and
Extended Hardware Modes, discrete pins are used
to configure and monitor the device. The Ex-
tended Hardware Mode provides a parallel chip
select input which latches the control inputs al-
lowing individual ICs to be configured using a
common set of control lines. In the Host Mode,
an external processor monitors and configures the
device through a serial interface. There are thir-
teen multi-function pins whose functionality is
determined by the operating mode. (see Table 2).
Hardware
Mode
Extended
Hardware
Mode
Host
Mode
Control
Method
Control
Pins
Control Pins
with Parallel
Chip Select
Serial
Interface
MODE
Pin
Level
<0.2 V Floating or
2.5 V
>(RV+)-0.2
V
Line
Coding
External Internal-
AMI, B8ZS,
or HDB3
External
AIS
Detection
No Yes No
Driver
Performance
Monitor
Yes No Yes
Table 1. Differences Between Operating Modes
CS61574A CS61575
DS154F3 9
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