xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 28 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
FMCON Program flash control (Read) E4H BUSY - - - HVA HVE SV OI 70 0111 0000
Program flash control (Write) E4H FMCMD.
7
FMCMD.
6
FMCMD.
5
FMCMD.
4
FMCMD.
3
FMCMD.
2
FMCMD.
1
FMCMD.
0
FMDATA Program flash data E5H 00 0000 0000
I2ADR I
2
C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 0000 0000
Bit address DF DE DD DC DB DA D9 D8
I2CON* I
2
C control register D8H - I2EN STA STO SI AA - CRSEL 00 x000 00x0
I2DAT I
2
C data register DAH
I2SCLH Serial clock generator/SCL
duty cycle register high
DDH 00 0000 0000
I2SCLL Serial clock generator/SCL
duty cycle register low
DCH 00 0000 0000
I2STAT I
2
C status register D9H STA.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 1111 1000
Bit address AF AE AD AC AB AA A9 A8
IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 0000 0000
Bit address EF EE ED EC EB EA E9 E8
IEN1* Interrupt enable 1 E8H EAD EST - - - EC EKBI EI2C 00
[1]
00x0 0000
Bit address BF BE BD BC BB BA B9 B8
IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00
[1]
x000 0000
IP0H Interrupt priority 0 high B7H - PWDRT
H
PBOH PSH/
PSRH
PT1H PX1H PT0H PX0H 00
[1]
x000 0000
Bit address FF FE FD FC FB FA F9 F8
IP1* Interrupt priority 1 F8H PAD PST - - - PC PKBI PI2C 00
[1]
00x0 0000
IP1H Interrupt priority 1 high F7H PADH PSTH - - - PCH PKBIH PI2CH 00
[1]
00x0 0000
KBCON Keypad control register 94H - -----PATN
_SEL
KBIF 00
[1]
xxxx xx00
KBMASK Keypad interrupt mask
register
86H 00 0000 0000
KBPATN Keypad pattern register FF 1111 1111
Table 9. P89LPC917 special function registers
…continued
* indicates SFRs that are bit addressable.
Name Description SFR
addr.
Bit functions and addresses Reset value
MSB LSB Hex Binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 29 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Bit address 87 86 85 84 83 82 81 80
P0* Port 0 80H T1/KB7/
CLKOUT
- CMPREF
/KB5
CIN1A
/KB4
CIN1B
/KB3
CIN2A
/KB2
CIN2B
/KB1
CMP2
/KB0
[1]
Bit address 97 96 95 94 93 92 91 90
P1* Port 1 90H - -
RST INT1 INT0/
SDA
T0/SCL RXD TXD
[1]
Bit address B7 B6 B5 B4 B3 B2 B1 B0
P0M1 Port 0 output mode 1 84H (P0M1.7) - (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF
[1]
1111 1111
P0M2 Port 0 output mode 2 85H (P0M2.7) - (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00
[1]
0000 0000
P1M1 Port 1 output mode 1 91H - - - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3
[1]
11x1 xx11
P1M2 Port 1 output mode 2 92H - - - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00
[1]
00x0 xx00
PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 0000 0000
PCONA Power control register A B5H RTCPD - VCPD ADPD I2PD - SPD - 00
[1]
0000 0000
Bit address D7 D6 D5 D4 D3 D2 D1 D0
PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 0000 0000
PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00 000x
RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX
[3]
RTCCON RTC control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60
[1][
6]
011x xx00
RTCH RTC register high D2H 00
[6]
0000 0000
RTCL RTC register low D3H 00
[6]
0000 0000
SADDR Serial port address register A9H 00 0000 0000
SADEN Serial port address enable B9H 00 0000 0000
SBUF Serial Port data buffer register 99H xx xxxx xxxx
Bit address 9F 9E 9D 9C 9B 9A 99 98
SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000
SSTAT Serial port extended status
register
BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000
SP Stack pointer 81H 07 0000 0111
TAMOD Timer 0 and 1 auxiliary mode 8FH - - - T1M2 - - - T0M2 00 xxx0 xxx0
Table 9. P89LPC917 special function registers
…continued
* indicates SFRs that are bit addressable.
Name Description SFR
addr.
Bit functions and addresses Reset value
MSB LSB Hex Binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 30 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
[1] All ports are in input only (high-impedance) state after power-up.
[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[3] The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx11 0000.
[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6] The only reset source that affects these SFRs is power-on reset.
Bit address 8F 8E 8D 8C 8B 8A 89 88
TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 0000 0000
TH0 Timer 0 high 8CH 00 0000 0000
TH1 Timer 1 high 8DH 00 0000 0000
TL0 Timer 0 low 8AH 00 0000 0000
TL1 Timer 1 low 8BH 00 0000 0000
TMOD Timer 0 and 1 mode 89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 0000 0000
TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0
[5] [6]
WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK
[4] [6]
WDL Watchdog load C1H FF 1111 1111
WFEED1 Watchdog feed 1 C2H
WFEED2 Watchdog feed 2 C3H
Table 9. P89LPC917 special function registers
…continued
* indicates SFRs that are bit addressable.
Name Description SFR
addr.
Bit functions and addresses Reset value
MSB LSB Hex Binary

P89LPC916FDH,129

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 2KB FLASH 16TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union