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P89LPC916FDH,129

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 43 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
8.19.10 The 9
th
bit (bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the TI interrupt.
If double buffering is enabled, TB must be updated before SBUF is written, as TB8 will be
double-buffered together with SBUF data.
8.20 I
2
C-bus serial interface
I
2
C-bus uses two wires (SDA and SCL) to transfer information between devices connected
to the bus, and it has the following features:
• Bidirectional data transfer between masters and slaves
• Multi master bus (no central master)
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
• The I
2
C-bus may be used for test and diagnostic purposes.
A typical I
2
C-bus configuration is shown in Figure 14. The P89LPC915/916/917 device
provides a byte-oriented I
2
C-bus interface that supports data transfers up to 400 kHz.
Fig 14. I
2
C-bus configuration
OTHER DEVICE
WITH I
2
C-BUS
INTERFACE
SDA
SCL
R
PU
R
PU
OTHER DEVICE
WITH I
2
C-BUS
INTERFACE
P1.3/SDA P1.2/SCL
I
2
C MCU
I
2
C-bus
002aab410
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 44 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Fig 15. I
2
C-bus serial interface block diagram
INTERNAL BUS
002aaa899
ADDRESS REGISTER
COMPARATOR
SHIFT REGISTER
8
I2ADR
ACK
BIT COUNTER /
ARBITRATION
AND SYNC LOGIC
8
I2DAT
TIMING
AND
CONTROL
LOGIC
SERIAL CLOCK
GENERATOR
CCLK
interrupt
INPUT
FILTER
OUTPUT
STAGE
INPUT
FILTER
OUTPUT
STAGE
P1.3
P1.3/SDA
P1.2/SCL
P1.2
timer 1
overflow
CONTROL REGISTERS AND
SCL DUTY CYCLE REGISTERS
I2CON
I2SCLH
I2SCLL
8
STATUS
DECODER
status bus
STATUS REGISTER
8
I2STAT
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 45 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
8.21 SPI
The P89LPC916 provides another high-speed serial communication interface—the SPI
interface. SPI is a full-duplex, high-speed, synchronous communication bus with two
operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in
Master mode or up to 3 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write
Collision Flag Protection.
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
• SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
• SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device
uses its SS pin to determine whether it is selected.
Typical connections are shown in Figure 17 through Figure 19.
Fig 16. SPI block diagram
002aaa900
CPU clock
DIVIDER
BY 4, 16, 64, 128
SELECT
CLOCK LOGIC
SPI CONTROL REGISTER
READ DATA BUFFER
8-BIT SHIFT REGISTER
SPI CONTROL
SPI STATUS REGISTER
SPR1
SPIF
WCOL
SPR0
SPI clock (master)
PIN
CONTROL
LOGIC
S
M
S
M
M
S
MISO
P2.3
MOSI
P2.2
SPICLK
P2.5
SS
P2.4
SPI
interrupt
request
internal
data
bus
SSIG
SPEN
SPEN
MSTR
DORD
MSTR
CPHA
CPOL
SPR1
SPR0
MSTR
SPEN
clock
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75

P89LPC916FDH,129

Mfr. #:
Buy P89LPC916FDH,129
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 2KB FLASH 16TSSOP
Lifecycle:
New from this manufacturer.
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