P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 66 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
12.2 ISP entry mode
Fig 27. Shift register mode timing
01234567
valid valid valid valid valid valid valid valid
T
XLXL
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set TI
set RI
t
XHQX
t
QVXH
t
XHDV
t
XHDX
clock
output data
write to SBUF
input data
clear RI
Fig 28. External clock timing
t
CHCL
t
CLCX
t
CHCX
T
cy(clk)
t
CLCH
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Table 18. Dynamic characteristics, ISP entry mode
V
DD
= 2.4 V to 3.6 V, unless otherwise specified.
T
amb
=
−
40
°
C to +85
°
C, or
−
40
°
C to +125
°
C (see Table 3 on page 3), unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
t
VR
V
DD
active to RST active delay time 50 - - µs
t
RH
RST HIGH time 1 - 32 µs
t
RL
RST LOW time 1 - - µs
Fig 29. ISP entry timing
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V
DD
RST
t
RL
t
VR
t
RH
