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ADUM240E1BRIZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
Data Sheet ADuM240D/ADuM240E/ADuM241D/ADuM241E/ADuM242D/ADuM242E
Rev. A | Page 7 of 26
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION
All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 2.5 V. Minimum/maximum specifications apply over the entire recommended
operation range: 2.25 V ≤ V
DD1
≤ 2.75 V, 2.25 V ≤ V
DD2
≤ 2.75 V, −40°C ≤ T
A
≤ +125°C, unless otherwise noted. Switching specifications
are tested with C
L
= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate
1
150 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
5.0 7.0 14 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 3 ns |t
PLH
− t
PHL
|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew t
PSK
6.8 ns
Between any two units at the same
temperature, voltage, and load
Channel Matching
Codirectional t
PSKCD
0.7 3.0 ns
Opposing Direction t
PSKOD
0.7 3.0 ns
Jitter 800 ps p-p See the Jitter Measurement section
190 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High V
IH
0.7 × V
DDx
V
Logic Low V
IL
0.3 × V
DDx
V
Output Voltage
Logic High V
OH
V
DDx
− 0.1 V
DDx
V I
Ox
2
= −20 µA, V
Ix
= V
IxH
3
V
DDx
− 0.4 V
DDx
− 0.2 V I
Ox
2
= −2 mA, V
Ix
= V
IxH
3
Logic Low V
OL
0.0 0.1 V I
Ox
2
= 20 µA, V
Ix
= V
IxL
4
0.2 0.4 V I
Ox
2
= 2 mA, V
Ix
= V
IxL
4
Input Current per Channel I
I
−10 +0.01 +10 µA 0 V ≤ V
Ix
≤ V
DDx
V
E2
Enable Input Pull-Up Current I
PU
−10 −3 µA V
E2
= 0 V
DISABLE
1
Input Pull-Down Current I
PD
9 15 µA DISABLE
1
= V
DDx
Tristate Output Current per Channel I
OZ
−10 +0.01 +10 µA 0 V ≤ V
Ox
≤ V
DDx
Quiescent Supply Current
ADuM240D/ADuM240E
I
DD1 (Q)
1.2 2.0 mA V
I
5
= 0 (E0, D0), 1 (E1, D1)
6
I
DD2 (Q)
2.0 2.64 mA V
I
5
= 0 (E0, D0), 1 (E1, D1)
6
I
DD1 (Q)
1.2 19.6 mA V
I
5
= 1 (E0, D0), 0 (E1, D1)
6
I
DD2 (Q)
2.0 2.76 mA V
I
5
= 1 (E0, D0), 0 (E1, D1)
6
ADuM241D/ADuM241E
I
DD1 (Q)
1.46 2.32 mA V
I
5
= 0 (E0, D0), 1 (E1, D1)
6
I
DD2 (Q)
1.75 2.47 mA V
I
5
= 0 (E0, D0), 1 (E1, D1)
6
I
DD1 (Q)
9.7 16.6 mA V
I
5
= 1 (E0, D0), 0 (E1, D1)
6
I
DD2 (Q)
5.67 9.67 mA V
I
5
= 1 (E0, D0), 0 (E1, D1)
6
ADuM242D/ADuM242E
I
DD1 (Q)
1.6 2.32 mA V
I
5
= 0 (E0, D0), 1 (E1, D1)
6
I
DD2 (Q)
1.6 2.32 mA V
I
5
= 0 (E0, D0), 1 (E1, D1)
6
I
DD1 (Q)
7.0 11.2 mA V
I
5
= 1 (E0, D0), 0 (E1, D1)
6
I
DD2 (Q)
7.0 11.2 mA V
I
5
= 1 (E0, D0), 0 (E1, D1)
6
Dynamic Supply Current
Dynamic Input I
DDI (D)
0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output I
DDO (D)
0.01 mA/Mbps Inputs switching, 50% duty cycle
ADuM240D/ADuM240E/ADuM241D/ADuM241E/ADuM242D/ADuM242E Data Sheet
Rev. A | Page 8 of 26
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Undervoltage Lockout
Positive V
DDx
Threshold V
DDxUV+
1.6 V
Negative V
DDx
Threshold V
DDxUV−
1.5 V
V
DDx
Hysteresis V
DDxUVH
0.1 V
AC SPECIFICATIONS
Output Rise/Fall Time t
R
/t
F
2.5 ns 10% to 90%
Common-Mode Transient Immunity
7
|CM
H
| 75 100 kV/µs
V
Ix
= V
DDx
, V
CM
= 1000 V,
transient magnitude = 800 V
|CM
L
| 75 100 kV/µs
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
1
150 Mbps is the highest data rate that can be guaranteed, although higher data rates are possible.
2
I
Ox
is the Channel x output current, where x = A, B, C, or D.
3
V
IxH
is the input side logic high.
4
V
IxL
is the input side logic low.
5
V
I
is the voltage input.
6
E0 is the ADuM240E0/ADuM241E0/ADuM242E0 models, D0 is the ADuM240D0/ADuM241D0/ADuM242D0 models, E1 is the ADuM240E1/ADuM241E1/ADuM242E1
models, and D1 is the ADuM240D1/ADuM241D1/ADuM242D1 models. See the Ordering Guide section.
7
|CM
H
| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (V
O
) > 0.8 V
DDx
. |CM
L
| is the maximum common-
mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 6. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
SUPPLY CURRENT
ADuM240D/ADuM240E
Supply Current Side 1 I
DD1
6.5 9.8 7.3 11.1 10.4 15.5 mA
Supply Current Side 2 I
DD2
2.0 3.6 3.3 5.2 7.3 10.2 mA
ADuM241D/ADuM241E
Supply Current Side 1 I
DD1
5.6 10.0 6.4 10.4 9.7 14.5 mA
Supply Current Side 2 I
DD2
3.8 6.55 4.8 7.7 8.3 11.5 mA
ADuM242D/ADuM242E
Supply Current Side 1 I
DD1
4.3 7.7 5.4 8.8 8.8 12.7 mA
Supply Current Side 2 I
DD2
5.0 8.4 6.1 9.5 9.5 13.4 mA
Data Sheet ADuM240D/ADuM240E/ADuM241D/ADuM241E/ADuM242D/ADuM242E
Rev. A | Page 9 of 26
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION
All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 1.8 V. Minimum/maximum specifications apply over the entire recommended
operation range: 1.7 V ≤ V
DD1
≤ 1.9 V, 1.7 V ≤ V
DD2
≤ 1.9 V, and −40°C ≤ T
A
≤ +125°C, unless otherwise noted. Switching specifications
are tested with C
L
= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 7.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate
1
150 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
5.8 8.7 15 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 3 ns |t
PLH
− t
PHL
|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew t
PSK
7.0 ns
Between any two units at the same
temperature, voltage, and load
Channel Matching
Codirectional t
PSKCD
0.7 3.0 ns
Opposing Direction t
PSKOD
0.7 3.0 ns
Jitter 470 ps p-p See the Jitter Measurement section
70 ps rms See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High V
IH
0.7 × V
DDx
V
Logic Low V
IL
0.3 × V
DDx
V
Output Voltage
Logic High V
OH
V
DDx
− 0.1 V
DDx
V I
Ox
2
= −20 µA, V
Ix
= V
IxH
3
V
DDx
− 0.4 V
DDx
− 0.2 V I
Ox
2
= −2 mA, V
Ix
= V
IxH
3
Logic Low V
OL
0.0 0.1 V I
Ox
2
= 20 µA, V
Ix
= V
IxL
4
0.2 0.4 V I
Ox
2
= 2 mA, V
Ix
= V
IxL
4
Input Current per Channel I
I
−10 +0.01 +10 µA 0 V ≤ V
Ix
≤ V
DDx
V
E2
Enable Input Pull-Up Current I
PU
−10 −3 µA V
E2
= 0 V
DISABLE
1
Input Pull-Down Current I
PD
9 15 µA DISABLE
1
= V
DDx
Tristate Output Current per Channel I
OZ
−10 +0.01 +10 µA 0 V ≤ V
Ox
≤ V
DDx
Quiescent Supply Current
ADuM240D/ADuM240E
I
DD1 (Q)
1.2 1.92 mA V
I
5
= 0 (E0, D0), 1 (E1, D1)
6
I
DD2 (Q)
2.0 2.64 mA V
I
5
= 0 (E0, D0), 1 (E1, D1)
6
I
DD1 (Q)
12.0 19.6 mA V
I
5
= 1 (E0, D0), 0 (E1, D1)
6
I
DD2 (Q)
2.0 2.76 mA V
I
5
= 1 (E0, D0), 0 (E1, D1)
6
ADuM241D/ADuM241E
I
DD1 (Q)
1.4 2.28 mA V
I
5
= 0 (E0, D0), 1 (E1, D1)
6
I
DD2 (Q)
1.73 2.45 mA V
I
5
= 0 (E0, D0), 1 (E1, D1)
6
I
DD1 (Q)
9.6 16.5 mA V
I
5
= 1 (E0, D0), 0 (E1, D1)
6
I
DD2 (Q)
5.6 9.6 mA V
I
5
= 1 (E0, D0), 0 (E1, D1)
6
ADuM242D/ADuM242E
I
DD1 (Q)
1.6 2.28 mA V
I
5
= 0 (E0, D0), 1 (E1, D1)
6
I
DD2 (Q)
1.6 2.28 mA V
I
5
= 0 (E0, D0), 1 (E1, D1)
6
I
DD1 (Q)
7.0 11.2 mA V
I
5
= 1 (E0, D0), 0 (E1, D1)
6
I
DD2 (Q)
7.0 11.2 mA V
I
5
= 1 (E0, D0), 0 (E1, D1)
6
Dynamic Supply Current
Dynamic Input I
DDI (D)
0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output I
DDO (D)
0.01 mA/Mbps Inputs switching, 50% duty cycle
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

ADUM240E1BRIZ

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Digital Isolators IC Robust Quad ISO 4:0 ch
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