MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
10 ______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1 ZCP
Zero-Inductor Current-Sense Comparator Input. The source voltage of the freewheeling FET (N4 in the Typical
Application Circuit) is sensed. The gate drive is terminated when this voltage becomes positive during a primary
power-OFF cycle.
2
ZCN
Zero-Inductor Current-Sense Comparator Negative Input
3
GND
Ground Connection
4 SFN
Negative Input of the Share-Force Amplifier. Connect the SFN inputs together from all the power-supply
secondaries, then connect to the load return terminal (isolated GND). Connect to GND when current sharing is not
used.
5 SFP
Positive Input of the Share-Force Amplifier. Connect the SFP pins together from all the power-supply secondaries.
Leave this pin unconnected when current sharing is not used.
6
COMPS
Compensation Output of the Load-Share Transconductance Amplifier
7 TSF Thermal Warning Flag Output
8
MRGU
Margin-Up Logic Input. When toggled high, the power-supply output voltage is set to the high margin.
9
MRGD
Margin-Down Logic Input. When toggled high, the power-supply output voltage is set to the low margin.
10
RMGD
Resistor Connection for Margin-Down
11
RMGU
Resistor Connection for Margin-Up
12
I
REF
Reference Current Output. A resistor from this current source output to GND sets the reference voltage used by
the error amplifier.
13
COMPV
Compensation Connection for the Error Amplifier. The feedback optocoupler LED is also connected to this point.
This open-drain output is capable of sinking at least 5mA.
14
INV
Inverting Input of the Error Amplifier. A voltage-divider connected to this input scales the power-supply output
voltage for regulation.
15
VSO
Output of the Remote-Sense Amplifier
16
VSN Negative Input of the Remote-Sense Amplifier. Connect this to the negative terminal of the load.
17
VSP Positive Input of the Remote-Sense Amplifier. Connect this to the positive terminal of the load.
18
CSO
Output of the Current-Sense Amplifier. It can be used to monitor the output current.
19
CSN
Connect this input to the negative terminal of the output current-sense resistor. Connect to GND when not used.
20
CSP Connect this input to the positive terminal of the output current-sense resistor. Connect to GND when not used.
21
VP
Compensation Pin for Internal +4V Preregulator. A minimum 1µF low-ESR capacitor must be connected to this pin
for bypassing.
22
V+
Supply Connection for the IC and Input to the Internal 5V (MAX5058) or 10V (MAX5059) Regulator. Maximum
voltage on this input is 28V.
23
V
REG
Regulated +5V (MAX5058) or +10V(MAX5059) Output Used by the Internal Circuitry and the Output Drivers. A
minimum 1µF capacitor must be connected to this pin for bypassing.
24
BUFIN
Input for the Synchronizing Pulse. This pulse is provided by the primary-side power IC.
25
VDR
Supply Connection for the Output Drivers. Can be connected to V
REG
for 5V (MAX5058) or 10V (MAX5059)
operation.
26
QREC
Driver Output for the Rectifying MOSFET
27
PGND
Power-Ground Connection. Return ground connection for the gate-driver pulse currents.
28
QSYNC
Driver Output for the Recirculating MOSFET
EP
Exposed Pad. This is the exposed pad on the underside of the IC. Connect the exposed paddle to GND and to a
large copper ground plane to aid in heat dissipation.
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
______________________________________________________________________________________ 11
30ns FALLING
EDGE DELAY
5mV
25
26
28
27
VDR
QREC
QSYNC
PGND
3
2
1
24
ZCP
BUFIN
ZCN
GND
SD DRIVERS
20ns
20ns
GATE-DRIVER BLOCK
17VSP
16
VSN
15
VSO
6COMPS
12I
REF
X1
RSA
REMOTE-SENSE AMPLIFIER BLOCK
14INV
13
COMPV
11
RMGU
E/A
ERROR AMPLIFIER BLOCK
I
REF
50μA
REFERENCE CURRENT BLOCK
42mV
0.5V
CURRENT-SHARE BLOCK
18
CSO
10
CSN
20
CSP
4
SFN
5
SFP
R
RR
R
SFA
X1
X2
V TO I
CAA
500μS
I = (1.15 x (V
CAA
- 1.25))μA
V
CAA
1.25V
10RMGD
9MRGD
8MRGU
MARGINING BLOCK
50kΩ
50kΩ
QMD
QMU
REGULATOR AND THERMAL MANAGEMENT BLOCK
MAX5058/MAX5059
LDO
5V/10V
PREG
4V
UVLO AND
THERMAL
SHUTDOWN
21
VP
22 V+
23
V
REG
7 TSF
SD DRIVERS
+125°C FLAG
Figure 1. MAX5058/MAX5059 Functional Diagram
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
12 ______________________________________________________________________________________
Detailed Description
The MAX5058/MAX5059 enable the design of high-effi-
ciency, isolated power supplies using synchronous rec-
tification on the secondary side. These devices
commutate the secondary-side MOSFETs by providing
a clean gate-drive signal that is synchronized to the
power MOSFET switching in the primary side of the iso-
lation transformer. Once fully enhanced, the secondary-
side MOSFETs have very low on-resistance, producing
a voltage drop much lower than Schottky diodes, result-
ing in much higher efficiencies. Simultaneous conduc-
tion of the synchronous rectifier MOSFETs is avoided by
having a look-ahead signal before the primary
MOSFETs turn on. This eliminates large current spikes
from a shorted transformer secondary.
The MAX5058 has a 5V internal gate-drive voltage reg-
ulator that can be used with logic-level MOSFETs. The
MAX5059 has a 10V internal gate-drive voltage regula-
tor that can be used with high-gate-voltage MOSFETs.
In addition to the gate drivers, there are blocks that
make the MAX5058/MAX5059 complete secondary-
side solutions. These blocks are as follows:
Regulator and thermal-management block
Buffer input and gate-driver block
Reference-current block
Error-amplifier block
Margining block
Remote-sense amplifier block
Current-share block
Regulators and Thermal Management
The linear regulators in the MAX5058/MAX5059 provide
power for the internal circuitry, as well as power for run-
ning the external synchronous MOSFETs. Design is sim-
plified by deriving the power from the secondary
winding before the output-filter inductor. The peak volt-
age at the secondary is at least twice the output volt-
age, yielding more than 7V peak even for output
voltages down to 3.3V. Use a diode and a capacitor to
rectify and filter the voltage before applying it to V+ (see
D6 and C32 in the Typical Application Circuit). The
input for the regulator is V+ and the output is V
REG
.
Connect VDR to V
REG
to provide the supply for the gate
driver’s QREC and QSYNC. For logic-level MOSFETs,
use the MAX5058. For conventional MOSFETs that
require 10V to be fully enhanced, use the MAX5059.
The V+ input voltage range is from +4.5V to +28V.
Supply enough current to this input to satisfy the quies-
cent supply current of the MAX5058/MAX5059, as well
as the current for the MOSFET drivers. Estimate the total
required supply current by using the following formula:
where I
V+
is the current that must be supplied into V+
and Q
N3
, Q
N4
are the total gate charges of MOSFETs
N3 and N4 in the Typical Application Circuit. f
SW
is the
switching frequency and I
SW
is the switching current of
the part. Use high-quality ceramic capacitors to bypass
V+ and V
REG
. Use additional capacitance as required
for bypassing switching currents generated by the dri-
vers when driving the chosen MOSFETs. Connect at
least a 1µF ceramic capacitor at the output of the regu-
lator V
REG
for stability.
The MAX5058/MAX5059 have an exposed pad at the
back of the package to enable heatsinking directly to a
ground plane. When soldered to a 1in
2
copper island,
these devices are able to dissipate approximately 1.9W
at +70°C ambient temperature. Connect the exposed
pad to the GND.
In addition to the regulators, this block contains a ther-
mal-shutdown circuit that shuts down the gate drivers if
the die temperature exceeds +160°C. This is a last
resort shutdown mechanism. The trigger of this shut-
down mechanism must be avoided. Turning off the
secondary synchronous rectifier drivers in this manner
while the output carries the full load current causes the
current to be diverted to the lossy external diodes or
body diodes of the MOSFETs. This, in most cases,
leads to rectifier failure due to power dissipation. To
prevent this, make use of the TSF output (temperature
warning flag). TSF is an open-drain output that gets
asserted when the die temperature exceeds +125°C,
well before the actual thermal shutdown at +160°C. An
optocoupler connected from V
REG
to the TSF pin can
provide a means for shutting down the switching at the
primary side, thus avoiding catastrophic failure.
Buffer Input (BUFIN) and MOSFET Drivers
The MAX5058/MAX5059 drive external N-channel
MOSFETs at QSYNC and QREC. The QSYNC output
drives the gate of the freewheeling MOSFET N4 in the
Typical Application Circuit. The QREC output drives the
gate of the rectifying MOSFET N3 in the Typical
Application Circuit. Each gate-driver output is capable
of sinking and sourcing up to 2A peak current,
enabling the MAX5058/MAX5059 to drive high-gate-
charge MOSFETs.
II f QQ
VSWSW N N+
=+× +
()
34

MAX5058EUI+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Gate Drivers Secondary Side Synch Rectifier Driver
Lifecycle:
New from this manufacturer.
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