Figure 8 shows a typical configuration with output volt-
ages high enough (V
OUT
> 2.5V) to allow a typical
optocoupler to be fully biased. In this case, there are
two feedback paths—one though the error amplifier
and one through the output-connected optocoupler.
This second feedback path must be considered when
compensating the overall feedback loop.
Figure 9 shows a typical configuration with an optocou-
pler for output voltages lower than 2.5V. In this case,
the direct connection of the optocoupler to the output is
not possible. There is only one feedback path and the
error-amplifier feedback network must be designed
accordingly.
Figure 10 shows the simplified block diagram for the
error amplifier.
Voltage Margining
The margining inputs MRGU (margin up) and MRGD
(margin down) control two internal MOSFETs with open-
drain outputs at RMGU and RMGD, respectively. When
margining is used, connect two pullup resistors from
RMGU and RMGD to I
REF
. A logic-high voltage at
MRGU causes QMU (see Figure 1) to open, increasing
the equivalent resistance at I
REF
and the reference volt-
age (V
IREF
). The error-amplifier inverting input, INV,
tracks I
REF
and forces the primary-side controller to
increase the output voltage. MRGD has the opposite
effect. When a logic high is applied to MRGD, QMD
turns on, decreasing the equivalent resistance at I
REF
and effectively reducing V
IREF
. This causes INV to track
and force the primary-side controller to reduce the out-
put voltage.
The margining inputs MRGU and MRGD are internally
pulled to GND with 40kΩ resistors. When margining is
not used, the inputs can be left floating or connected to
GND to make V
IREF
= 50µA × R12.
Calculation Procedure for Output-Voltage Setting
Resistors and Margining
Use the following step-by-step procedure to calculate
the output-voltage setting and margining resistors (see
the Typical Application Circuit):
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
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