MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
______________________________________________________________________________________ 19
Figure 13. Paralleling Multiple Power-Supply Modules for Current Sharing
CSN
CSP
V
OUT
+V
IN+
VSP
V
IN-
VSN
V
OUT-
SYNCIN
SFN
STARTUP
SFP
SYNCOUT
MAX5051
MAX5058
MAX5059
ORAND
POWER MODULE
MRGU MRGD
CSN
CSP
V
OUT
+V
IN+
VSP
V
IN-
VSN
V
OUT-
SYNCIN
SFN
STARTUP
SFP
SYNCOUT
MAX5051
MAX5058
MAX5059
ORAND
POWER MODULE
MRGU MRGD
CSN
CSP
V
OUT
+V
IN+
VSP
V
IN-
VSN
V
OUT-
SYNCIN
SFN
STARTUP
SFP
SYNCOUT
MAX5051
MAX5058
MAX5059
ORAND
POWER MODULE
MRGU MRGD
LOAD
V
IN+
V
IN-
36V TO 72V
When the MAX5051 is used as the primary-side con-
troller, additional benefits are also realized with its spe-
cial paralleling pins. The MAX5051 allows simultaneous
shutdown and wake-up, as well as frequency synchro-
nization and 180 degree out-of-phase operation of
each connected primary.
The current-share loop consists of the following func-
tional blocks:
A diode ORed force amplifier that connects with the
other modules and forces the bus to carry a voltage
proportional to the highest current among the mod-
ules.
A sense amplifier that senses this share-bus volt-
age and applies it to internal circuitry.
A fixed gain of 20, current-sense amplifier that
senses the output current through a sense resistor.
A current-adjust amplifier that functions as an error-
amplifier block in the current-share loop.
A voltage-to-current (VtoI) block that adds a small
amount of current to the reference current, increas-
ing the reference voltage and enabling the module
to share more current.
The adjustment range and thus the sharing capability of
the modules is limited by the amount of additional out-
put voltage boost possible through the VtoI block. The
typical voltage boost is +3% (i.e., 1.5µA/50µA). Figure
14 shows the transfer function of the VtoI block. This
adjustment range also sets a limit on the amount of volt-
age drop allowed for current sharing. For effective cur-
rent sharing, the sum of all voltage drops must be kept
below 3% and the output-to-load connection drop of
each power module must be kept equal.
Current-sharing functions follow:
The voltage across the current-sense resistor for each
module is sensed and compared to the voltage on the
current-share bus. The voltage on the current-share bus
represents the current from the module that has the high-
est output current compared to the other modules. Each
module compares its current to this maximum current. If
its current is less than the maximum, then the module
increases its reference current with the VtoI block. This
raises the reference voltage presented at the noninvert-
ing input of the error amplifier. With a higher reference
voltage, the output voltage of the module rises in an
attempt to increase its output current. This process con-
tinues until the currents balance between the modules.
The current-adjust amplifier (see Figure 1) has an offset
at its inverting input that requires the share-bus voltage
to reach 40mV before the current-share control loop
attempts to regulate the output-load-current balance.
Thus, the current-share regulation does not begin until
the current-sense signals have exceeded 2mV (i.e.,
42mV/20).
Figure 15 shows the simplified equivalent small-signal
circuit of the current-share control loop. The current-
adjust amplifier represents the error amplifier in this
loop. The command signal, which is the voltage across
the SFP and SFN pins, is applied to the noninverting
input of this amplifier. For small-signal analysis, the
noninverting pin is shown grounded in Figure 15. This is
a low-bandwidth loop.
Assuming a much smaller unity-gain crossover bandwidth
(f
CS
) for the current-share loop compared to the main out-
put-voltage-regulation loop (i.e., f
CS
<< f
C
), the open-loop
gain of the current-share loop can be written as:
where f
CS
is the unity-gain crossover frequency of the
current-share loop (typically 10Hz to 100Hz), f
C
is the
unity-gain crossover frequency of the main output loop,
G
PS
(s) is the gain of the power stage from the refer-
ence voltage input of the error amplifier to the output
(G
PS
= V
OUT
/V
IREF
), R
S
is the current-sense resistor,
and R
LOAD
is the load resistance. Note that the current-
share loop bandwidth is highest for the lowest value of
R
LOAD
(maximum load).
Gs G s
Gs
sC
GsR
Gs
R
RR
T SFA
CAA
COMPS
VtoI IREF
PS
S
S LOAD
() ()
()
()
()
×
××
()
××
+
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
20 ______________________________________________________________________________________
1.5μA
1.25V
V
CAA
V TO I
SLOPE = 1.15μA/V
Figure 14. Transfer Function Curve of the V to I Block
CSA
CAA
V TO I
PWM STAGE
AND FILTERS
FEEDBACK
NETWORK
V
OUT
R
S
R
LOAD
R
IREF
C
COMPS
E/A
+ V
SENSE
-
G
PS
(s)
G
CAA
(s)
G
CSA
(s)
G
V TO I
(s)
Figure 15. Small-Signal Equivalent Current-Share Control Loop
Figure 16 shows the idealized small-signal response of
the Typical Application Circuit from the noninverting
input of the error amplifier to the output. This response
shows that the unity-gain crossover frequency of the
current-share loop can easily be placed between 10Hz
and 100Hz, while at the same time avoiding interaction
with the main voltage-control loop.
For frequencies below 100Hz, G
T
(s) can be written as
(using the DC gain value for G
PS
(s)):
Equating |G
T
| = 1 and solving for C
COMPS
yields:
The current-sharing loop is compensated with a capac-
itor from COMPS to GND. This results in a dominant
pole that forces the loop gain of the current-share loop
to cross 0dB with a single pole (20dB/decade) rolloff.
When R
LOAD
>> R
S
, the above can be simplified further.
Example:
R
S
= 2mΩ
V
OUT
= 3.3V
f
CS
= 10Hz
R
LOAD
= 0.22Ω
The resulting overall open-loop response of the current-
share control loop is shown in Figure 17.
Applications Information
Isolated 48V Input Power Supply
Figure 18 shows a complete design of an isolated syn-
chronously rectified power supply with a +36V to +75V
telecom input voltage range. This design uses the
MAX5051 as the primary-side controller and the
MAX5058 as the secondary-side synchronous rectifier
driver. Figures 19 though 24 show some of the perfor-
mance aspects of this power-supply design. This
power supply can sustain a continuous short circuit at
its output terminals. This circuit is available as a com-
pletely built and tested evaluation kit (MAX5058EVKIT).
C
FHzV V
Hz
F
COMPS
=
×
()
×
()
×
()
()
×
()
36 61 0 002 3 3
10 0 22
011
./. .
.
.
μ
μ
Ω
Ω
C
FHzV R V
fR
COMPS
S OUT
CS LOAD
=
×
()
××
×
36 61./μ
C
FHzV R V
fRR
COMPS
S OUT
CS S LOAD
=
×
()
××
×+
()
36 61./μ
Gs
S
sC
AV R
V
V
R
RR
T
COMPS
IREF
OUT
IREF
S
S LOAD
() . /
()
×
×
()
×
××
+
20
500
115
μ
μ
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
______________________________________________________________________________________ 21
POWER-STAGE GAIN/PHASE
FREQUENCY (Hz)
GAIN (dB/DIV)
1k10010
-15
-10
-5
0
5
10
15
20
-20
1 10k
PHASE (DEGREES/div)
-45
0
45
90
-90
GAIN
PHASE
Figure 16. Idealized (with Ideal Power Stage and Optocoupler)
Frequency Response (G
PS
(s)) from Noninverting Input of the
Error Amplifier to the Output of the Power Supply for the
Typical Application Circuit of Figure 18
FREQUENCY (Hz)
GAIN (dB/DIV)
1k10010
-60
-40
-20
0
20
40
60
80
-80
1 10k
PHASE (DEGREES/div)
-90
0
90
180
-180
GAIN
PHASE
135
45
-45
-135
Figure 17. Overall Open-Loop Response of the Current-Share
Loop

MAX5058EUI+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Gate Drivers Secondary Side Synch Rectifier Driver
Lifecycle:
New from this manufacturer.
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