NCP81233
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39
either VCC5V or EN toggled state. The OTP assertion
threshold VOTP and reset threshold VOTP_RST can be
calculated by:
V
OTP
+
V
REF
) I
OTP_HYS
R
OTP1
1 )
R
OTP1
R
OTP2
(eq. 21)
V
OTP_RST
+
V
REF
R
OTP2
R
OTP1
) R
OTP2
(eq. 22)
The corresponding OTP temperature TOTP and reset
temperature T
OTP_RST
can be calculated by
T
OTP
+
1
ln
ǒ
R
NTC_OTP
ń
R
TNC
Ǔ
B
)
1
25)273.15
* 273.15
(eq. 23)
T
OTP_RST
+
1
ln
ǒ
R
NTC_OTPRST
ń
R
TNC
Ǔ
B
)
1
25)273.15
* 273.15
(eq. 24)
Where:
R
NTC_OTP
+
1
1
R
T_OTP
*R
T1
*
1
R
T2
(eq. 25)
R
NTC_OTPRST
+
1
1
R
T_OTPRST
*R
T1
*
1
R
T2
(eq. 26)
R
T_OTP
+
ǒ
V
REF
V
OTP
* 1
Ǔ
R
T3
(eq. 27)
R
T_OTPRST
+
ǒ
V
REF
V
OTP_RST
* 1
Ǔ
R
T3
(eq. 28)
With OTP Configuration 2, as shown in Figure 18 (2), the
NCP81233 receives an external signal VT linearly
representing temperature and compares to an internal 0.6 V
reference voltage. If the voltage is over the threshold OTP
happens. The OTP assertion threshold V
OTP
and reset
threshold V
OTP_RST
in this configuration can be obtained by
V
T_OTP
+
ǒ
1 )
R
OTP1
R
OTP2
Ǔ
0.6
(eq. 29)
V
T_OTP_RST
+
ǒ
0.6
R
OTP2
* I
OTP_HYS
Ǔ
R
OTP1
) 0.6
(eq. 30)
OTP detection starts from the beginning of soft-start time
T
SS
, and ends in shutdown, latch-off, and idle time of hiccup
mode.
Thermal Shutdown (TSD)
The NCP81233 has an internal thermal shutdown
protection to protect the device from overheating in an
extreme case that the die temperature exceeds 150
°
C. TSD
detection is activated when VCC5V, EN, and DRVON are
valid. Once the thermal protection is triggered, the whole
chip shuts down and all PWM signals are in high impedance.
If the temperature drops below 125
°
C, the system
automatically recovers and a normal power sequence
follows.
I
2
C Interface
Control of the NCP81233 is carried out using the I
2
C
Interface. The NCP81233 is connected to this bus as a slave
device, under the control of a master controller. The master
controller can start to access the NCP81233 via I
2
C after
VCC5V is ready for more than 2 ms.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, because a low-to-high
transition when the clock is high might be interpreted as a
stop signal. The number of data bytes that can be transmitted
over the serial bus in a single read or write operation is
limited only by what the master and slave devices can
handle.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the tenth clock pulse to assert a stop
condition. In read mode, the master device overrides the
acknowledge bit by pulling the data line high during the low
period before the ninth clock pulse; this is known as No
Acknowledge. The master takes the data line low during the
low period before the tenth clock pulse, and then high during
the tenth clock pulse to assert a stop condition.
Any number of bytes of data can be transferred over the
serial bus in one operation, but it is not possible to mix read
and write in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation.
In the NCP81233, write operations contain one, two or
three bytes, and read operations contain one or two bytes.
The command code or register address determines the
number of bytes to be read or written, See the register map
for more information.
To write data to one of the device data registers or read
data from it, the address pointer register must be set so that
the correct data register is addressed (i.e. command code),
and then data can be written to that register or read from it.
The first byte of a read or write operation always contains an
address that is stored in the address pointer register. If data
is to be written to the device, the write operation contains a
