NCP81233
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7. The master sends the 7 bit slave address followed
by the read bit (high).
8. The slave asserts ACK on SDA.
9. The slave sends the first Data Byte (low Data
Byte).
10. The master asserts ACK on SDA.
11. The slave sends the second Data Byte (high Data
Byte).
12. The master asserts a No ACK on SDA.
13. The master asserts a stop condition on SDA and
the transaction ends.
Figure 27. Single Word Read to a Register
SLAVE
ADDRESS
W A
SLAVE
ADDRESS
SAA
COMMAND
CODE
23156784
DATA
(LSB)
A
910
S
R
PA
DATA
(MSB)
11
12 13
Block Read
In this operation, the master device sends a command
byte, the slave sends a byte count followed by the stated
number of data bytes to the master device as follows:
1. The master device asserts a START condition on
SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a REPEATED START condition
on SDA
5. The master sends the 7-bit slave address followed
by the read bit (high).
6. The slave asserts ACK on SDA.
7. The slave sends the byte count N.
8. The master asserts ACK on SDA.
9. The slave sends the first data byte.
10. The master asserts ACK on SDA.
11. The slave sends the remainder of the data byes, the
master asserts an ACK on SDA after each data
byte.
12. After the last data byte the master asserts a No
ACK on SDA.
13. The master asserts a STOP condition on SDA.
Figure 28. Block Write to a Command Coder
SLAVE
ADDRESS
W A
BYTE
COUNT=N
SA
SLAVE
ADDRESS
2315
6
7
8
4
9
PA
DATA
BYTE N
A
DATA
BYTE 1
10
11
12
13
S
R
A
ALERT# Signal
The NCP81233 has an ALERT# output to notify the host
of fault or warning conditions and also supports the Alert
Response Address (ARA) protocol. ALERT# pin is an
open-drain output. It is pulled low whenever at least one bit
in the status registers is asserted with the following
exception, on condition that the corresponding alert is not
masked in the Mask Alert register. Bit 6 in Status Byte and
Bit 3 in the high byte of Status Word have no impact on
ALERT#.
A broadcast address used by the system host as part of the
Alert Response Protocol initiated when a device asserts the
ALERT# signal. The Alert Response Address (0001 100b)
can be a substitute for device master capability. The host
processes the interrupt and simultaneously accesses all
ALERT# devices through the Alert Response Address. Only
the device(s) which pulled ALERT# low will acknowledge
the Alert Response Address. The host performs a modified
Receive Byte operation. The 7 bit device address provided
by the slave transmit device is placed in the 7 most
significant bits of the byte. The eighth bit can be a zero or
one.
Figure 29. Alert Response Address Command
Alert Response AddressSRdP
N
XAddressA
711711
If more than one device pulls ALERT# low, the highest
priority (lowest address) device will win communication
rights via standard arbitration during the slave address
transfer. A host which does not implement the ALERT#
signal may periodically access the ARA.
Timeout
The NCP81233 includes a timeout feature. If there is no
activity for 35 ms, the NCP81233 assumes that the bus is
locked and releases the bus. This prevents the device from
locking or holding the expecting data. Some controllers
cannot handle the timeout feature, so it can be disabled.
Configuration Register 1 (0xD1)
Bit 3 BUS_TO_EN = 1; timeout enabled.
Bit 3 TODIS = 0; timeout disabled (default).
Virus Protection
To prevent rogue programs or viruses from accessing
critical NCP81233 register settings, the lock bit can be set.
Setting Bit 0 of the Lock/Reset sets the lock bit and locks
critical registers. In this mode, certain registers can no
longer be written to until the NCP81233 is powered down
and powered up again. For more information on which
registers are locked see the register map.
