IDT
®
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor 0743H—03/15/13
ICS932S208
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
10
Electrical Characteristics - REF-14.318MHz
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
= 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Long Accuracy
pp
m
1
see Tperiod min-max values -300 300 ppm
Clock period
T
p
eriod
14.318MHz output nominal 69.8270 69.8550 ns
Output High Voltage
V
OH
1
I
OH
= -1 mA
2.4 V
Output Low Voltage
V
OL
1
I
OL
= 1 mA
0.4 V
Output High Current
I
OH
1
V
OH
@MIN = 1.0 V, V
OH
@MAX = 3.135 V
-29 -23 mA
Output Low Current
I
OL
1
V
OL
@MIN = 1.95 V, V
OL
@MAX = 0.4 V
29 27 mA
Rise Time
t
r1
1
V
OL
= 0.4 V, V
OH
= 2.4 V
12ns
Fall Time
t
f1
1
V
OH
= 2.4 V, V
OL
= 0.4 V
12ns
Skew
t
sk1
1
V
T
= 1.5 V
500 ps
Duty Cycle
d
t1
1
V
T
= 1.5 V
45 55 %
Jitter
t
j
c
y
c-c
y
c
1
V
T
= 1.5 V
1000 ps
1
Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
Group to Group Skews at Common Transition Edges
GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS
200MHZ CPU to 3V66
1
S
CPU200-3V66
3V66 (4:0) leads 200MHZ
CPU
-2.0 -1.5 -1.0 ns
3V66 to PCI
S
3V66-PCI
3V66 (4:0) leads 33MHz PCI 1.50 3.50 ns
DOT-USB
S
DOT_USB
180 degrees out of phase 0.00 1.00 ns
DOT-VCH
S
DOT_VCH
in phase 0.00 1.00 ns
1. 3V66 MHz C
L
= 0pf, Rseries = 33 ohm. CPU CL = 2 pf, Rseries = 33 ohm, Rshunt = 49.9 ohms.
Measured at the pins of the 932S208.
IDT
®
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor 0743H—03/15/13
ICS932S208
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
11
General I
2
C serial interface information for the ICS932S208
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge
each byte
one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
IDT
®
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor 0743H—03/15/13
ICS932S208
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
12
I
2
C Table: Read-Back Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
RESERVED RESERVED - X
Bit 6
RESERVED RESERVED - X
Bit 5
RESERVED RESERVED - X
Bit 4
RESERVED RESERVED - X
Bit 3
RESERVED RESERVED - X
Bit 2
RESERVED RESERVED - X
Bit 1
FSB
Freq Select 1 Read
Back
RX
Bit 0
FSA
Freq Select 0 Read
Back
RX
I
2
C Table: Spreading and Device Behavior Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
SRC/SRC#
SRC Free-Running
Control
RW FREE-RUN STOPPABLE 0
Bit 6
SRC Output Control RW Disable Enable 1
Bit 5
RESERVED RESERVED - X
Bit 4
RESERVED RESERVED - X
Bit 3
RESERVED RESERVED - X
Bit 2
CPUT2/CPUC2 Output Control RW Disable Enable 1
Bit 1
CPUT1/CPUC1 Output Control RW Disable Enable 1
Bit 0
CPUT0/CPUC0 Output Enable RW Disable Enable 1
I
2
C Table: Output Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
SRC_PD#
Drive Mode
0: Driven in PD# RW Driven Hi-Z 0
Bit 6
SRC_Stop#
Drive Mode
0: Driven in
PCI_Stop#
RW Driven Hi-Z 0
Bit 5
CPUT2_PD# Drive
Mode
RW Driven Hi-Z 0
Bit 4
CPUT1_PD# Drive
Mode
RW Driven Hi-Z 0
Bit 3
CPUT0_PD# Drive
Mode
RW Driven Hi-Z 0
Bit 2
RESERVED RESERVED - X
Bit 1
RESERVED RESERVED - X
Bit 0
RESERVED RESERVED - X
41, 40
-
-
-
-
47, 46
47, 46
44, 43
38, 37
38, 37
-
44, 43
41, 40
B
y
te 2
38, 37
38, 37
-
B
y
te 0
-
-
-
RESERVED
RESERVED
- RESERVED
-
-
-
RESERVED
0:driven in PD#
1: Tri-stated
-
RESERVED
READBACK of CPU(3:0)
Frequency
RESERVED
B
y
te 1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED

932S208DGLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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