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932S208DGLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
IDT
®
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor 0743H—03/15/13
ICS932S208
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
13
I
2
C Table: Output Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
PCI_Stop#
PCI_Stop# Control
0:all stoppable PCI
are stopped
RW Enable Disable 1
Bit 6
PCICLK6 Output Control RW Disable Enable 1
Bit 5
PCICLK5 Out
p
ut Control RW Disable Enable 1
Bit 4
PCICLK4 Out
p
ut Control RW Disable Enable 1
Bit 3
PCICLK3 Out
p
ut Control RW Disable Enable 1
Bit 2
PCICLK2 Output Control RW Disable Enable 1
Bit 1
PCICLK1 Output Control RW Disable Enable 1
Bit 0
PCICLK0 Output Control RW Disable Enable 1
I
2
C Table: Output Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
48MHz_USB
2x output drive
0=2x drive RW 2x drive normal 1
Bit 6
48MHz_USB Output Control RW Disable Enable 1
Bit 5
PCIF2 RW FREE-RUN STOPPABLE 0
Bit 4
PCIF1 RW FREE-RUN STOPPABLE 0
Bit 3
PCIF0 RW FREE-RUN STOPPABLE 0
Bit 2
PCICLK_F2 Output Control RW Disable Enable 1
Bit 1
PCICLK_F1 Output Control RW Disable Enable 1
Bit 0
PCICLK_F0 Output Control RW Disable Enable 1
I
2
C Table: Output Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
48MHZ_DOT Output Control RW Disable Enable 1
Bit 6
CPUT3/CPUC3 Output Control RW Disable Enable 1
Bit 5
3V66_4/VCH
Select
Output Select RW 3V66 VCH 0
Bit 4
3V66_4/VCH Output Control RW Disable Enable 1
Bit 3
3V66_3 Output Control RW Disable Enable 1
Bit 2
3V66_2 Output Control RW Disable Enable 1
Bit 1
3V66_1 Output Control RW Disable Enable 1
Bit 0
3V66_0 Output Control RW Disable Enable 1
7
50/49
29
29
27
23
22
18
15
14
26
B
y
te 5
32
9
13
12
8
B
y
te 3
7,8,9,12,13,14,15,
18,19,20,37,38,
20
19
7
9
8
PCI FREE-RUN
NING CONTROL
B
y
te 4
31
31
IDT
®
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor 0743H—03/15/13
ICS932S208
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
14
I
2
C Table: Output Control and Fix Frequency Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
Test Clock Mode Test Clock Mode RW Disable Enable 0
Bit 6
RESERVED - - - - 0
Bit 5
FS Testmode
FS_A and FS_B
Operation
RW Normal Test Mode 0
Bit 4
SRC100#
SRC Frequency
Select
RW 100MHz 200MHz 0
Bit 3
RESERVED - - - - 0
Bit 2
SSEN
Spread Spectrum
Enable
RW
Spread
OFF
Spread
ON
0
Bit 1
REF1 Output Control RW Disable Enable 1
Bit 0
REF0 Output Control RW Disable Enable 1
I
2
C Table: Vendor & Revision ID Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
RID3 R - - X
Bit 6
RID2 R - - X
Bit 5
RID1 R - - X
Bit 4
RID0 R - - X
Bit 3
VID3 R - - 0
Bit 2
VID2 R - - 0
Bit 1
VID1 R - - 0
Bit 0
VID0 R - - 1
-
VENDOR ID
-
-
-
B
y
te 7
-
REVISION ID
-
-
-
1
37,38
7,8,9,12,13,14,15,1
8,19,20,22,23,26,27
,29,31,32,37,38,40,
41,43,44,46,47
2
-
40,41,43,44,46,47
1,2,7,8,9,12,13,14,
15,18,19,20,22,23,2
6,27,29,31,32,37,38
,40,41,43,44,46,47
B
y
te 6
IDT
®
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor 0743H—03/15/13
ICS932S208
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
15
The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to
be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the
PCI_STOP register bit.
PCI Stop Functionality
#POTS_ICPUPC#UPCCRS#CRS66V3ICP/FICPTOD/BSUFERetoN
1lamroNlamroNlamroNlamroNzHM66zHM33zHM84zHM813.41
0lamroNlamroN6*ferI
taolFro
woLzHM66woLzHM84zHM813.41
The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all
PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low,
the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and
the SRC# will latch low as shown below.
PCI_STOP#
Tsu
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# Assertion (transition from '1' to '0')
The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After
detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free
manner.
PCI_STOP#
Tsu
Tdrive_SRC
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# - De-assertion
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

932S208DGLFT

Mfr. #:
Buy 932S208DGLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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