932S208DGLFT Datasheet 932S208DGLFT, 932S208DGLF, 932S208DFLFT | P16-P18

IDT

Programmable Timing Control Hub

for Next Gen P4

Processor 0743H—03/15/13

ICS932S208

Programmable Timing Control Hub

for Next Gen P4

Processor

PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power.

When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start

without glitches.

PD#, Power Down

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Notes:

1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation.

2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses.

PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be

held low on their next high to low transition.

All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register

determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.

When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at

2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.

PWRDWN#

CPU, 133MHz

CPU#, 133MHz

SRC, 100MHz

SRC#, 100MHz

3V66, 66MHz

USB, 48MHz

PCI, 33MHz

REF, 14.31818

PD# Assertion

IDT

Programmable Timing Control Hub

for Next Gen P4

Processor 0743H—03/15/13

ICS932S208

Programmable Timing Control Hub

for Next Gen P4

Processor

The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive

mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of

200mV in less than 300μs of PD# deassertion.

PWRDWN#

Tstable

<1.8mS

Tdrive_PwrDwn#

<300μS, >200mV

CPU, 133MHz

CPU#, 133MHz

SRC, 100MHz

SRC# 100MHz

3V66, 66MHz

USB, 48MHz

PCI, 33MHz

REF, 14.31818

PD# De-assertion

The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is

3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The output

will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising

edge of DOT_48 clock.

3V66

3V66_4/VCH

DOT_48

7.49nS min

3V66_4/VCH Pin Functionality

IDT

Programmable Timing Control Hub

for Next Gen P4

Processor 0743H—03/15/13

ICS932S208

Programmable Timing Control Hub

for Next Gen P4

Processor

To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or

tristated during PwrDwn# and CPU_Stop# mode and the SRC clock is configurable to be driven or tristated during

PCI_Stop# and PwrDwn# mode. Each differential clock (SRC, CPU[2:0]) output can be disabled by setting the

corresponding output's register OE bit to "0" (disable). Disabled outputs are to be tristated regardless of "CPU_Stop",

"SRC_Stop" and "PwrDwn" register bit settings.

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Notes:

1. Each output has four corresponding control register bits, OE, PwrDwn, CPU_Stop and "Free Running"

2. Iref x 6 and Iref x 2 is the output current in the corresponding mode

3. See Control Registers section for bit address

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Notes:

1. SRC output has four corresponding control register bits, OE, PwrDwn, SRC_Stop and "Free Running"

2. Iref x 6 and Iref x 2 is the output current in the corresponding mode

3. See Control Registers section for bit address

Differential Clock Tristate

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

932S208DGLFT

Mfr. #:

Buy 932S208DGLFT

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK

Lifecycle:

New from this manufacturer.

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932S208DGLFT

932S208DGLFT

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