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932S208DGLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
IDT
®
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor 0743H—03/15/13
ICS932S208
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
4
General Description
Block Diagram
Power Groups
ICS932S208 follows Intel CK409B Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS932S208 is driven with a 14.318MHz crystal. It generates CPU outputs
up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.
I REF
PLL2
Frequency
Dividers
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
48MHz, USB, DOT
X1
X2
XTAL
SDATA
SCLK
Vtt_PWRGD#
PD#
FS_A
FS_B
Control
Logic
REF (1:0)
CPUCLKT (3:0)
CPUCLKC (3:0)
SRCCLKT0
SRCCLKC0
3V66(4:0)
PCICLK (6:0)
PCICLKF (2:0)
VDD GND
3 6 Xtal, Ref
24 25 3V66 [0:4]
10,16 11,17 PCICLK outputs
36 39 SRCCLK outputs
55 54 Master clock, CPU Analog
34 33 48MHz, PLL
N/A 53 IREF
48, 42 45 CPUCLK clocks
Description
Pin Number
IDT
®
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor 0743H—03/15/13
ICS932S208
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
5
Absolute Maximum Ratings
Symbol Parameter Min Max Units
VDD_A 3.3V Core Supply Voltage V
DD
+ 0.5V V
VDD_In 3.3V Logic Input Supply Voltage GND - 0.5 V
DD
+ 0.5V V
Ts Storage Temperature -65 150
°
C
Tambient Ambient Operating Temp 0 70 °C
Tcase Case Temperature 115 °C
ESD prot
I
nput
ESD
protect
i
on
human body model
2000 V
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage
V
IH
3.3 V +/-5% 2
V
DD
+ 0.3
V
Input MID Voltage
V
MID
3.3 V +/-5% 1 1.8 V
Input Low Voltage
V
IL
3.3 V +/-5%
V
SS
- 0.3
0.8 V
Input High Current
I
IH
V
IN
= V
DD
-5 5 uA
I
IL1
V
IN
= 0 V; Inputs with no pull-up
resistors
-5 uA
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200 uA
Operating Supply Current
I
DD3.3OP
Full Active, C
L
= Full load;
350 mA
all diff
p
airs driven 35 mA
all differential
p
airs tri-stated 12 mA
In
p
ut Fre
q
uenc
y
3
F
i
V
DD
= 3.3 V
14.31818 MHz 3
Pin Inductance
1
L
pin
7nH1
C
IN
Logic Inputs 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
C
INX
X1 & X2 pins 5 pF 1
Clk Stabilization
1,2
T
STAB
From V
DD
Power-Up or de-
assertion of PD# to 1st clock
1.8 ms 1,2
Modulation Fre
q
uenc
y
Trian
g
ular Modulation 30 33 kHz 1
Tdrive_SRC
SRC output enable after
PCI_Sto
p
# de-assertion
15 ns 1
Tdrive_PD#
CPU output enable after
PD# de-assertion
300 us 1
Tfall_Pd# PD# fall time of 5 ns 1
Trise_Pd# PD# rise time of 5 ns 2
Tdrive_CPU_Stop#
CPU output enable after
CPU_Sto
p
# de-assertion
10 us 1
Tfall_CPU_Sto
p
# PD# fall time of 5 ns 1
Trise_CPU_Stop# PD# rise time of 5 ns 2
1
Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
2
See timin
g
dia
g
rams for timin
g
re
q
uirements.
I
DD3.3PD
3
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
pp
m fre
q
uenc
y
accurac
y
on PLL out
p
uts.
Input Capacitance
1
Input Low Current
Powerdown Current
IDT
®
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor 0743H—03/15/13
ICS932S208
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
6
Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output
Im
p
edance
Zo
1
V
O
= V
x
3000
1
Output High Voltage
V
OH3
I
OH
= -1 mA
2.4 V
Output Low Voltage
V
OL3
I
OL
= 1 mA
0.4
Voltage High VHigh 660 850 1
Voltage Low VLow -150 150 1
Max Volta
g
eVovs 1150 1
Min Volta
g
e Vuds -300 1
Crossin
g
Volta
g
e
(
abs
)
Vcross
(
abs
)
250 550 mV 1
Crossing Voltage (var) d-Vcross
Variation of crossing over all
ed
g
es
140 mV 1
Lon
g
Accurac
y
pp
m see T
p
eriod min-max values -300 300
pp
m1,2
200MHz nominal 4.9985 5.0015 ns 2
200MHz s
p
read 4.9985 5.0266 ns 2
166.66MHz nominal 5.9982 6.0018 ns 2
166.66MHz s
p
read 5.9982 6.0320 ns 2
133.33MHz nominal 7.4978 7.5023 ns 2
133.33MHz s
p
read 7.4978 5.4000 ns 2
100.00MHz nominal 9.9970 10.0030 ns 2
100.00MHz s
p
read 9.9970 10.0533 ns 2
200MHz nominal 4.8735 ns 1,2
166.66MHz nominal/s
p
read 5.8732 ns 1,2
133.33MHz nominal/s
p
read 7.3728 ns 1,2
100.00MHz nominal/s
p
read 9.8720 ns 1,2
Rise Time
t
r
V
OL
= 0.175V, V
OH
= 0.525V
175 700 ps 1
Fall Time
t
f
V
OH
= 0.525V V
OL
= 0.175V
175 700 ps 1
Rise Time Variation
d-t
r
125 ps 1
Fall Time Variation
d-t
f
125 ps 1
Duty Cycle
d
t3
Measurement from differential
wavefrom
45 55 % 1
Skew
t
sk3
V
T
= 50%
100 ps 1
Jitter, Cycle to cycle
t
jcyc-cyc
Measurement from differential
wavefrom
125 ps 1
1
Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
SRC clock outputs run at onl
y
100MHz or 200MHz, specs for 133.33 and 166.66 do not appl
y
to SRC clock pair.
Statistical measurement on single
ended signal using oscilloscope
math function.
mV
Measurement on single ended
signal using absolute value.
mV
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
TperiodAverage period
Absolute min period
T
absmin
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

932S208DGLFT

Mfr. #:
Buy 932S208DGLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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