Memory Block Depth (bits) Programmable Width
4K x5, x4
8K x2
16K x1
Clock Networks and PLL Clock Sources
The clock network architecture is based on Intel's global, regional, and peripheral
clock structure. This clock structure is supported by dedicated clock input pins,
fractional clock synthesis PLLs, and integer I/O PLLs.
Clock Networks
The Intel Cyclone 10 GX core clock networks are capable of up to 300 MHz fabric
operation across the full industrial temperature range. For the external memory
interface, the clock network supports the hard memory controller with speeds up to
1,866 Mbps in a quarter-rate transfer.
To reduce power consumption, the IntelQuartus Prime Pro Edition software identifies
all unused sections of the clock network and powers them down.
Fractional Synthesis and I/O PLLs
Intel Cyclone 10 GX devices contain up to 4 fractional synthesis PLLs and up to 6 I/O
PLLs that are available for both specific and general purpose uses in the core:
• Fractional synthesis PLLs—located in the column adjacent to the transceiver blocks
• I/O PLLs—located in each bank of the 48 I/Os
Fractional Synthesis PLLs
You can use the fractional synthesis PLLs to:
• Reduce the number of oscillators that are required on your board
• Reduce the number of clock pins that are used in the device by synthesizing
multiple clock frequencies from a single reference clock source
The fractional synthesis PLLs support the following features:
• Reference clock frequency synthesis for transceiver CMU and Advanced Transmit
(ATX) PLLs
• Clock network delay compensation
• Zero-delay buffering
• Direct transmit clocking for transceivers
• Independently configurable into two modes:
— Conventional integer mode equivalent to the general purpose PLL
— Enhanced fractional mode with third order delta-sigma modulation
• PLL cascading
Intel
®
Cyclone
®
10 GX Device Overview
C10GX51001 | 2018.07.11
Intel
®
Cyclone
®
10 GX Device Overview
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