DK-DEV-10CX220-A Datasheet 10CX085YU484I6G, 10CX220YF780E6G, 10CX085YU484E6G | P16-P18

Low Power Serial Transceivers

Intel Cyclone 10 GX FPGAs offer transceivers that deliver high bandwidth, throughput,

and low latency at very low power consumption per channel. The transceivers support

various data rates from 125 Mbps up to 12.5 Gbps in chip-to-chip applications.

• 10 Gbps transceivers at as low as 168 mW

• 6 Gbps transceivers at as low as 117 mW

The combination of 20 nm process technology and architectural advances provide the

following benefits:

• Significant reduction in die area and power consumption

• Increase of up to two times in transceiver I/O density compared to previous

generation devices while maintaining optimal signal integrity

• Up to 12 transceiver channels

• All channels feature continuous data rate support up to the maximum rated speed

Figure 4. Intel Cyclone 10 GX Transceiver Block Architecture

ATX

PLL

fPLL

ATX

PLL

FPGA

Fabric

PCS

Transceiver PMA TX/RX

Flexible Clock Distribution Network

Transceiver Channels

All transceiver channels feature a dedicated Physical Medium Attachment (PMA) and a

hardened Physical Coding Sublayer (PCS).

Intel

Cyclone

10 GX Device Overview

C10GX51001 | 2018.07.11

Intel

Cyclone

10 GX Device Overview

• The PMA provides primary interfacing capabilities to physical channels.

• The PCS typically handles encoding/decoding, word alignment, and other pre-

processing functions before transferring data to the FPGA core fabric.

A transceiver channel consists of a PMA and a PCS block. Most transceiver banks have

6 channels. There are some transceiver banks that contain only 4 channels.

A wide variety of bonded and non-bonded data rate configurations is possible using a

highly configurable clock distribution network.

Figure 5. Device Chip Overview for Intel Cyclone 10 GX Devices

This figure is a graphical representation of a top view of the silicon die, which corresponds to a reverse view for

flip chip packages. Different Intel Cyclone 10 GX devices may have different floorplans than the one shown in

this figure.

Core Logic Fabric

M20K Internal Memory BlocksM20K Internal Memory Blocks

Variable Precision DSP Blocks

I/O PLLs

Hard Memory Controllers, General-Purpose I/O Cells, LVDS

M20K Internal Memory BlocksM20K Internal Memory Blocks

Variable Precision DSP Blocks

Core Logic Fabric

I/O PLLs

Hard Memory Controllers, General-Purpose I/O Cells, LVDS

M20K Internal Memory BlocksM20K Internal Memory Blocks

Variable Precision DSP Blocks

Transceiver Channels

Hard IP Per Transceiver: Standard PCS and Enhanced PCS Hard IPs

PCI Express Gen2 Hard IP

Fractional PLLs

Hard PCS

Transceiver PMA

Transceiver Clock Networks

fPLL

ATX (LC)

Transmit

PLL

fPLL

ATX (LC)

Transmit

PLL

fPLL

ATX (LC)

Transmit

PLL

Unused transceiver channels

can be used as additional

transceiver transmit PLLs

PMA Features

Intel Cyclone 10 GX transceivers provide exceptional signal integrity at data rates up

to 12.5 Gbps. Clocking options include ultra-low jitter ATX PLLs (LC tank based), clock

multiplier unit (CMU) PLLs, and fractional PLLs.

Each transceiver channel contains a channel PLL that can be used as the CMU PLL or

clock data recovery (CDR) PLL. In CDR mode, the channel PLL recovers the receiver

clock and data in the transceiver channel.

Table 12. PMA Features of the Transceivers in Intel Cyclone 10 GX Devices

Feature Capability

Chip-to-Chip Data Rates 125 Mbps to 12.5 Gbps

Backplane Support Drive backplanes at data rates up to 6.6 Gbps

Optical Module Support SFP+/SFP, XFP, CXP, QSFP/QSFP28, CFP/CFP2/CFP4

continued...

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10 GX Device Overview

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Intel

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10 GX Device Overview

Feature Capability

Cable Driving Support SFP+ Direct Attach, PCI Express over cable, eSATA

Transmit Pre-Emphasis 4-tap transmit pre-emphasis and de-emphasis to compensate for system channel loss

Continuous Time Linear

Equalizer (CTLE)

High-gain linear receive equalization to compensate for system channel loss

Variable Gain Amplifier Optimizes the signal amplitude prior to the CDR sampling and operates in fixed and

adaptive modes

Precision Signal Integrity

Calibration Engine (PreSICE)

Hardened calibration controller to quickly calibrate all transceiver control parameters on

power-up, which provides the optimal signal integrity and jitter performance

Advanced Transmit (ATX)

PLL

Low jitter ATX (LC tank based) PLLs with continuous tuning range to cover a wide range of

standard and proprietary protocols

Fractional PLLs On-chip fractional frequency synthesizers to replace on-board crystal oscillators and reduce

system cost

Digitally Assisted Analog

CDR

Superior jitter tolerance with fast lock time

Dynamic Reconfiguration Allows independent control of the Avalon memory-mapped interface of each transceiver

channel for the highest transceiver flexibility

Multiple PCS-PMA and PCS-

PLD interface widths

8-, 10-, 16-, 20-, 32-, 40-, or 64-bit interface widths for flexibility of deserialization width,

encoding, and reduced latency

PCS Features

You can use the transceiver PCS to support a wide range of protocols ranging from

125 Mbps to 12.5 Gbps.

Table 13. PCS Features of the Transceivers in Intel Cyclone 10 GX Devices

This table summarizes the Intel Cyclone 10 GX transceiver PCS features.

PCS

Description

Standard PCS • Operates at a data rate up to 12.5 Gbps

• Supports protocols such as PCI-Express, CPRI 4.2+, and GigE

• Implements other protocols using Basic/Custom (Standard PCS) transceiver

configuration rules.

Enhanced PCS • Performs functions common to most serial data industry standards, such as word

alignment, encoding/decoding, and framing, before data is sent or received off-chip

through the PMA

• Handles data transfer to and from the FPGA fabric

• Handles data transfer internally to and from the PMA

• Provides frequency compensation

• Performs channel bonding for multi-channel low skew applications

PCIe Gen2 PCS • Supports the seamless switching of Data and Clock between the Gen1 and Gen2 data

rates

• Provides support for PIPE 3.0 features

• Supports the PIPE interface with the Hard IP enabled, as well as with the Hard IP

bypassed

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10 GX Device Overview

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Intel

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10 GX Device Overview

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Programmable Logic IC Development Tools Cyclone 10 GX Development Kit

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