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DK-DEV-10CX220-A

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
I/O PLLs
The integer mode I/O PLLs are located in each bank of 48 I/Os. You can use the I/O
PLLs to simplify the design of external memory and high-speed LVDS interfaces.
In each I/O bank, the I/O PLLs are adjacent to the hard memory controllers and LVDS
SERDES. Because these PLLs are tightly coupled with the I/Os that need to use them,
it makes it easier to close timing.
You can use the I/O PLLs for general purpose applications in the core such as clock
network delay compensation and zero-delay buffering.
Intel Cyclone 10 GX devices support PLL-to-PLL cascading.
FPGA General Purpose I/O
Intel Cyclone 10 GX devices offer highly configurable GPIOs. Each I/O bank contains
48 general purpose I/Os and a high-efficiency hard memory controller.
The following list describes the features of the GPIOs:
• Consist of 3 V I/Os for high-voltage application and LVDS I/Os for differential
signaling
— One 3 V I/O bank that supports up to 3 V I/O standards
— LVDS I/O banks that support up to 1.8 V I/O standards
• Support a wide range of single-ended and differential I/O interfaces
• LVDS speeds up to 1.434 Gbps
• Each LVDS pair of pins has differential input and output buffers, allowing you to
configure the LVDS direction for each pair.
• Programmable bus hold and weak pull-up
• Programmable differential output voltage (V
OD
) and programmable pre-emphasis
• Series (R
S
) and parallel (R
T
) on-chip termination (OCT) for all I/O banks with OCT
calibration to limit the termination impedance variation
• On-chip dynamic termination that has the ability to swap between series and
parallel termination, depending on whether there is read or write on a common
bus for signal integrity
• Easy timing closure support using the hard read FIFO in the input register path,
and delay-locked loop (DLL) delay chain with fine and coarse architecture
Related Information
I/O and Differential I/O Buffers in Intel Cyclone 10 GX Devices, Intel Cyclone 10 GX
Core Fabric and General Purpose I/Os Handbook
Provides more information about the GPIOs in Intel Cyclone 10 GX devices.
External Memory Interface
Intel Cyclone 10 GX devices offer external memory bandwidth of up to 1×72-bit or
2×40-bit DDR3 memory interfaces running at up to 1,866 Mbps. This bandwidth
provides ease of design, lower power, and resource efficiencies of hardened high-
performance memory controllers.
Intel
®
Cyclone
®
10 GX Device Overview
C10GX51001 | 2018.07.11
Intel
®
Cyclone
®
10 GX Device Overview
13
The memory interface within Intel Cyclone 10 GX FPGAs delivers the highest
performance and ease of use. You can configure up to a maximum width of 72 bits
when using the hard memory controllers.
Each I/O contains a hardened DDR read/write path (PHY) capable of performing key
memory interface functionality such as read/write leveling, FIFO buffering to lower
latency and improve margin, timing calibration, and on-chip termination.
The timing calibration is aided by the inclusion of hard microcontroller based on Intel's
Nios
®
II technology, specifically tailored to control the calibration of multiple memory
interfaces. This calibration allows the Intel Cyclone 10 GX device to compensate for
any changes in process, voltage, or temperature either within the Intel Cyclone 10 GX
device itself, or within the external memory device. The advanced calibration
algorithms ensure maximum bandwidth and robust timing margin across all operating
conditions.
Memory Standards Supported by Intel Cyclone 10 GX Devices
The I/Os are designed to provide high performance support for existing and emerging
external memory standards.
Table 11. Memory Standards Supported by the Hard Memory Controller
This table lists the capability of the hard memory controller and the maximum speed achievable in different I/O
bank types. For specific details, refer to the External Memory Interface Spec Estimator and Intel Cyclone 10 GX
Device Datasheet.
Memory
Standard
Rate Support Device Speed
Grade
Ping Pong PHY
Support
Frequency (MHz)
LVDS I/O Bank 3 V I/O Bank
DDR3 SDRAM Half rate –5 Yes 533 225
— 533 225
–6 Yes 466 166
— 466 166
Quarter rate –5 Yes 933 450
933 450
–6 Yes 933 333
933 333
DDR3L SDRAM Half rate –5 Yes 533 225
— 533 225
–6 Yes 466 166
— 466 166
Quarter rate –5 Yes 933 450
— 933 450
–6 Yes 933 333
— 933 333
LPDDR3 Half rate –5 — 400 225
continued...
Intel
®
Cyclone
®
10 GX Device Overview
C10GX51001 | 2018.07.11
Intel
®
Cyclone
®
10 GX Device Overview
14
Memory
Standard
Rate Support Device Speed
Grade
Ping Pong PHY
Support
Frequency (MHz)
LVDS I/O Bank 3 V I/O Bank
–6 — 333 166
Quarter rate –5 — 800 450
–6 — 666 333
PCIe Gen1 and Gen2 Hard IP
Intel Cyclone 10 GX devices contain PCIe hard IP that is designed for performance and
ease-of-use:
• Includes all layers of the PCIe stack—transaction, data link and physical layers.
• Supports PCIe Gen2 Endpoint and Root Port in x1, x2, or x4 lane configuration
(5)
.
• Operates independently from the core logic—optional configuration via protocol
(CvP) allows the PCIe link to power up and complete link training in less than
100 ms while the Intel Cyclone 10 GX device completes loading the programming
file for the rest of the FPGA.
• Provides improved end-to-end datapath protection using ECC.
• Supports FPGA configuration via protocol (CvP) using PCIe at Gen2 or Gen1 speed.
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet
Interlaken Support
The Intel Cyclone 10 GX enhanced PCS hard IP provides integrated Interlaken PCS
supporting rates up to 12.5 Gbps per lane.
The Interlaken PCS is based on the proven functionality of the PCS developed for
Intel’s previous generation FPGAs, which demonstrated interoperability with Interlaken
ASSP vendors and third-party IP suppliers. The Interlaken PCS is present in every
transceiver channel in Intel Cyclone 10 GX devices.
10 Gbps Ethernet Support
The Intel Cyclone 10 GX enhanced PCS hard IP supports 10GBASE-R PCS compliant
with IEEE 802.3 10 Gbps Ethernet (10GbE). The integrated hard IP support for 10GbE
and the 10 Gbps transceivers save external PHY cost, board space, and system power.
The scalable hard IP supports multiple independent 10GbE ports while using a single
PLL for all the 10GBASE-R PCS instantiations, which saves on core logic resources and
clock networks. This simplifies multiport 10GbE systems compared to XAUI interfaces
that require an external XAUI-to-10G PHY.
(5)
For the PCIe hard IP, only x2 lane configuration is available for the U484 package of the
10CX085, 10CX105, 10CX150, and 10CX220 devices, and the F672 package of the 10CX085
device.
Intel
®
Cyclone
®
10 GX Device Overview
C10GX51001 | 2018.07.11
Intel
®
Cyclone
®
10 GX Device Overview
15
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DK-DEV-10CX220-A

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Buy DK-DEV-10CX220-A
Manufacturer:
Intel
Description:
Programmable Logic IC Development Tools Cyclone 10 GX Development Kit
Lifecycle:
New from this manufacturer.
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