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DK-DEV-10CX220-A

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PCS Protocol Support
Table 14. Protocols Supported by Intel Cyclone 10 GX Transceiver PCS
This table lists some of the protocols supported by the Intel Cyclone 10 GX transceiver PCS.
Protocol Data Rate (Gbps) Transceiver IP PCS Support
PCIe Gen2 x1, x2, x4 5.0 Native PHY (PIPE) Standard PCS
PCIe Gen1 x1, x2, x4 2.5 Native PHY (PIPE) Standard PCS
1000BASE-X Gigabit Ethernet 1.25 Native PHY Standard PCS
1000BASE-X Gigabit Ethernet with IEEE 1588v2 1.25 Native PHY Standard PCS
10GBASE-R 10.3125 Native PHY Enhanced PCS
10GBASE-R with IEEE 1588v2 10.3125 Native PHY Enhanced PCS
Interlaken (CEI-6G-SR/CEI-11G-SR) 3.125 to 12.5 Native PHY Enhanced PCS
SFI-S/SFI-5.2 6.25 Native PHY Enhanced PCS
12G SDI 11.88 Native PHY Enhanced PCS
CPRI 6.0 (64B/66B) 0.6144 to 6.144 Native PHY Enhanced PCS
CPRI 4.2 (8B/10B) 0.6144 to 6.144 Native PHY Standard PCS
OBSAI RP3 v4.2 0.6144 to 6.144 Native PHY Standard PCS
SD-SDI/HD-SDI/3G-SDI 0.143
(6)
to 2.97 Native PHY Standard PCS
Dynamic Reconfiguration
The Intel Cyclone 10 GX devices support dynamic reconfiguration. You can use
dynamic reconfiguration to enable seamless reconfiguration of the transceivers.
You can reconfigure the PMA and PCS blocks while the device continues to operate.
This feature allows you to change the data rates, protocol, and analog settings of a
channel in a transceiver bank without affecting on-going data transfer in other
transceiver banks. This feature is ideal for applications that require dynamic
multiprotocol or multirate support.
(6)
The 0.143 Gbps data rate is supported using oversampling of user logic that you must
implement in the FPGA fabric.
Intel
®
Cyclone
®
10 GX Device Overview
C10GX51001 | 2018.07.11
Intel
®
Cyclone
®
10 GX Device Overview
19
Enhanced Configuration and Configuration via Protocol
Table 15. Configuration Schemes and Features of Intel Cyclone 10 GX Devices
Intel Cyclone 10 GX devices support 1.8 V programming voltage and several configuration schemes.
Scheme Data Width Max Clock
Rate
(MHz)
Max Data Rate
(Mbps)
(7)
Decompression Design
Security
(8)
Remote
System
Update
JTAG 1 bit 33 33 — — —
Active Serial (AS)
through the EPCQ-L
configuration device
1 bit,
4 bits
100 400 Yes Yes Yes
Passive serial (PS)
through CPLD or
external
microcontroller
1 bit 100 100 Yes Yes Parallel
Flash Loader
(PFL) IP
core
Fast passive parallel
(FPP) through CPLD or
external
microcontroller
8 bits 100 3200 Yes Yes PFL IP core
16 bits Yes Yes
32 bits Yes Yes
Configuration via
Protocol [CvP (PCIe)]
x1, x2, x4
lanes
— 5000 Yes Yes —
You can configure Intel Cyclone 10 GX devices through PCIe using Configuration via
Protocol (CvP). The Intel Cyclone 10 GX CvP implementation conforms to the PCIe
100 ms power-up-to-active time requirement.
SEU Error Detection and Correction
Intel Cyclone 10 GX devices offer robust and easy-to-use single-event upset (SEU)
error detection and correction circuitry.
The detection and correction circuitry includes protection for Configuration RAM
(CRAM) programming bits and user memories. The CRAM is protected by a
continuously running CRC error detection circuit with integrated ECC that
automatically corrects one or two errors and detects higher order multi-bit errors.
When more than two errors occur, correction is available through reloading of the core
programming file, providing a complete design refresh while the FPGA continues to
operate.
The physical layout of the Intel Cyclone 10 GX CRAM array is optimized to make the
majority of multi-bit upsets appear as independent single-bit or double-bit errors
which are automatically corrected by the integrated CRAM ECC circuitry. In addition to
the CRAM protection, the M20K memory blocks also include integrated ECC circuitry
and are layout-optimized for error detection and correction. The MLAB does not have
ECC.
(7)
Enabling either compression or design security features affects the maximum data rate. Refer
to the Intel Cyclone 10 GX Device Datasheet for more information.
(8)
Encryption and compression cannot be used simultaneously.
Intel
®
Cyclone
®
10 GX Device Overview
C10GX51001 | 2018.07.11
Intel
®
Cyclone
®
10 GX Device Overview
20
Power Management
Intel Cyclone 10 GX devices leverage the advanced 20 nm process technology, a low
0.9 V core power supply, an enhanced core architecture, and several optional power
reduction techniques to reduce total power consumption.
Intel Cyclone 10 GX devices use Programmable Power Technology for power reduction.
The IntelQuartus Prime Pro Edition software identifies non-critical timing paths and
biases the logic in these paths for low power instead of high performance
Furthermore, Intel Cyclone 10 GX devices feature Intel’s industry-leading low power
transceivers and include a number of hard IP blocks that not only reduce logic
resources but also deliver substantial power savings compared to soft
implementations. In general, hard IP blocks consume up to 90% less power than the
equivalent soft logic implementations.
Incremental Compilation
The IntelQuartus Prime Pro Edition software incremental compilation feature reduces
compilation time and helps preserve performance to ease timing closure.
Incremental compilation supports top-down, bottom-up, and team-based design flows.
This feature facilitates modular, hierarchical, and team-based design flows where
different designers compile their respective design sections in parallel. Furthermore,
different designers or IP providers can develop and optimize different blocks of the
design independently. These blocks can then be imported into the top level project.
Document Revision History for Intel Cyclone 10 GX Device
Overview
Document
Version
Changes
2018.07.11 Removed mentions of Single Root I/O Virtualization (SR-IOV). The Intel Cyclone 10 GX devices do not
support SR-IOV.
2018.05.07 Added footnote to the PCIe hard IP topic to list device and package combinations that support only x2
lane configuration.
Date Version Changes
November 2017 2017.11.06 • The document is no longer preliminary.
• Updated the 10 Gbps Ethernet Support section.
• Updated the features supported in the PMA Features of the Transceivers
in Intel Cyclone 10 GX Devices table.
• Removed automotive support.
• Removed the note about the migration paths in the I/O Vertical
Migration for Intel Cyclone 10 GX Devices.
May 2017 2017.05.08 Initial release.
Intel
®
Cyclone
®
10 GX Device Overview
C10GX51001 | 2018.07.11
Intel
®
Cyclone
®
10 GX Device Overview
21
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DK-DEV-10CX220-A

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Buy DK-DEV-10CX220-A
Manufacturer:
Intel
Description:
Programmable Logic IC Development Tools Cyclone 10 GX Development Kit
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