3/57
M36W432T, M36W432B
Figure10.FlashWriteACWaveforms,WriteEnableControlled ..........................26
Table16.FlashWriteACCharacteristics,WriteEnableControlled........................27
Figure 11. Flash Write AC Waveforms, Chip Enable Controlled ...........................28
Table 17. Flash Write AC Characteristics, Chip Enable Controlled. . .......................29
Figure12.FlashPower-UpandResetACWaveforms..................................30
Table18.FlashPower-UpandResetACCharacteristics................................30
Figure 13. SRAM Read AC Waveforms, Address Controlled with UBS = LBS = V
IL
...........31
Figure14.SRAMReadACWaveforms,E1S,E2SorGSControlled.......................31
Figure 15. SRAM Standby AC Waveforms . ..........................................32
Table19.SRAMReadACCharacteristics...........................................32
Figure16.SRAMWriteACWaveforms,WSControlledwithGSLow ......................33
Figure17.SRAMWriteACWaveforms,WSControlledwithGSHigh......................33
Figure18.SRAMWriteACWaveforms,UBSandLBSControlled.........................34
Figure19.SRAMWriteACWaveforms,E1SControlled ................................34
Table20.SRAMWriteACCharacteristics...........................................35
Figure 20. SRAM Low V
DDS
DataRetentionACWaveforms,E1SControlled................36
Figure 21. SRAM Low V
DDS
DataRetentionACWaveforms,E2SControlled................36
Table 21. SRAM Low V
DDS
DataRetentionCharacteristic...............................36
PACKAGE MECHANICAL . . . .......................................................37
Figure22.StackedLFBGA66-8x8ballarray,0.8mmpitch,BottomViewPackageOutline....37
Table 22. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Package Mechanical Data . . . ....37
Figure 23. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package) . 38
Figure 24. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)39
PARTNUMBERING ...............................................................40
Table23.OrderingInformationScheme.............................................40
Table24.DaisyChainOrderingScheme............................................40
REVISIONHISTORY...............................................................41
Table25.DocumentRevisionHistory...............................................41
APPENDIXA.FLASHMEMORYBLOCKADDRESSTABLES .............................42
Table 26. Top Boot Block Addresses, M36W432T . ....................................42
Table27.BottomBootBlockAddresses,M36W432B ..................................43
APPENDIXB.COMMONFLASHINTERFACE(CFI) .....................................44
Table28.QueryStructureOverview................................................44
Table 29. CFI Query Identification String . . ..........................................44
Table30.CFIQuerySystemInterfaceInformation.....................................45
Table31.DeviceGeometryDefinition...............................................46
Table 32. Primary Algorithm-Specific Extended Query Table .............................47
Table33.SecurityCodeArea.....................................................48
APPENDIXC.FLASHMEMORYFLOWCHARTSandPSEUDOCODES.....................49
