M36W432T, M36W432B
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OPERATING MODES
Flash Bus Operations
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and Re-
set. See Table 2, Main Operation Modes, for a
summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Read. Read Bus operations are used to output
the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common
Flash Interface. Both Chip Enable and Output En-
ablemustbeatV
IL
in order to perform a read op-
eration. The Chip Enable input should be used to
enable the device. Output Enable should be used
to gate data onto the output. The data read de-
pends on the previous command written to the
memory (see Command Interface section). See
Figure 9, Read Mode AC Waveforms, and Table
15, Flash Read AC Characteristics, for details of
when the output becomes valid.
Read mode is the default state of the device when
exiting Reset or after power-up.
Write. Bus Write operations write Commands to
the memory or latch Input Data to be programmed.
A write operation is initiated when Chip Enable
and Write Enable are at V
IL
with Output Enable at
V
IH
. Commands, Input Data and Addresses are
latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.
See Figures 10 and 11, Write AC Waveforms, and
Tables 16 and 17, Flash Write AC Characteristics,
for details of the timing requirements.
Output Disable. The data outputs are high im-
pedance when the Output Enable is at V
IH
.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
when Chip Enable is at V
IH
andthedeviceisin
read mode. The power consumption is reduced to
the stand-by level and the outputs are set to high
impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
V
IH
during a program or erase operation, the de-
vice enters Standby mode when finished.
Automatic Standby. Automatic Standby pro-
vides a low power consumption state during Read
mode. Following a read operation, the device en-
ters Automatic Standby after 150ns of bus inactiv-
ity even if Chip Enable is Low, V
IL
, and the supply
current is reduced to I
DD1
. The data Inputs/Out-
puts will still output data if a bus Read operation is
in progress.
Reset. During Reset mode when Output Enable
is Low, V
IL
, the memory is deselected and the out-
puts are high impedance. The memory is in Reset
mode when Reset is at V
IL
. The power consump-
tion is reduced to the Standby level, independently
from the Chip Enable, Output Enable or Write En-
able inputs. If Reset is pulled to V
SSF
during a Pro-
gram or Erase, this operation is aborted and the
memory content is no longer valid.
Flash Command Interface
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings and verifies the correct execution
of the Program and Erase commands. The Pro-
gram/Erase Controller provides a Status Register
whose output may be read at any time during, to
monitor the progress of the operation, or the Pro-
gram/Erase states. See Appendix 29, Table 34,
Write State Machine Current/Next, for a summary
of the Command Interface.
The Command Interface is reset to Read mode
when power is first applied, when exiting from Re-
set or whenever V
DDF
is lower than V
LKO
.Com-
mand sequences must be followed exactly. Any
invalid combination of commands will reset the de-
vice to Read mode. Refer to Table 3, Commands,
in conjunction with the text descriptions below.
Read Memory Array Command. The Read
command returns the memory to its Read mode.
One Bus Write cycle is required to issue the Read
Memory Array command and return the memory to
Read mode. Subsequent read operations will read
the addressed location and output the data. When
a device Reset occurs, the memory defaults to
Read mode.
Read Status Register Command. The Status
Register indicates when a program or erase oper-
ation is complete and the success or failure of the
operation itself. Issue a Read Status Register
command to read the Status Register’s contents.
Subsequent Bus Read operations read the Status
Register at any address, until another command is
issued. See Table 10, Status Register Bits, for de-
tails on the definitions of the bits.
The Read Status Register command may be is-
sued at any time, even during a Program/Erase
operation. Any Read attempt during a Program/
Erase operation will automatically output the con-
tent of the Status Register.
