M36W432T85ZA6T Datasheet M36W432T85ZA6T | P19-P21

19/57

M36W432T, M36W432B

Flash Status Register

The Status Register provides information on the

current or previous Program or Erase operation.

The various bits convey information and errors on

the operation. To read the Status register the

Read Status Register command can be issued, re-

fer to Read Status Register Command section. To

output the contents, the Status Register is latched

on the falling edge of the Chip Enable or Output

Enable signals, and can be read until Chip Enable

or Output Enable returns to V

. Either Chip En-

able or Output Enable must be toggled to update

the latched data.

Bus Read operations from any address always

read the Status Register during Program and

Erase operations.

The bits in the Status Register are summarized in

Table 10, Status Register Bits. Refer to Table 10

in conjunction with the following text descriptions.

Program/Erase Controller Status (Bit 7). The Pro-

gram/Erase Controller Status bit indicates whether

the Program/Erase Controller is active or inactive.

When the Program/Erase Controller Status bit is

Low (set to ‘0’), the Program/Erase Controller is

active; when the bit is High (set to ‘1’), the Pro-

gram/Erase Controller is inactive, and the device

is ready to process a new command.

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High.

During Program, Erase, operations the Program/

EraseControllerStatusbitcanbepolledtofindthe

end of the operation. Other bits in the Status Reg-

ister should not be tested until the Program/Erase

Controller completes the operation and the bit is

High.

After the Program/Erase Controller completes its

operation the Erase Status, Program Status, V

PPF

Status and Block Lock Status bits should be tested

for errors.

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status bit indicates that an Erase operation

has been suspended or is going to be suspended.

When the Erase Suspend Status bit is High (set to

‘1’), a Program/Erase Suspend command has

been issued and the memory is waiting for a Pro-

gram/Erase Resume command.

The Erase Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is High (Program/Erase Controller inactive).

Bit 7 is set within 30µs of the Program/Erase Sus-

pend command being issued therefore the memo-

ry may still complete the operation rather than

entering the Suspend mode.

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has failed to verify

that the block has erased correctly. When the

Erase Status bit is High (set to ‘1’), the Program/

Erase Controller has applied the maximum num-

ber of pulses to the block and still failed to verify

that the block has erased correctly. The Erase Sta-

tus bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

Once set High, the Erase Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Status (Bit 4). The Program Status bit

is used to identify a Program failure. When the

Program Status bit is High (set to ‘1’), the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the byte and still failed to ver-

ify that it has programmed correctly. The Program

Status bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new command is issued, otherwise the new

command will appear to fail.

PPF

Status (Bit 3). The V

PPF

Status bit can be

used to identify an invalid voltage on the V

PPF

during Program and Erase operations. The V

PPF

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

cur if V

PPF

becomes invalid during an operation.

When the V

PPF

Status bit is Low (set to ‘0’), the

voltageontheV

PPF

pin was sampled at a valid

voltage; when the V

PPF

Status bit is High (set to

‘1’), the V

PPF

pin has a voltage that is below the

PPF

Lockout Voltage, V

PPLK

, the memory is pro-

tected and Program and Erase operations cannot

be performed.

Once set High, the V

PPF

Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

M36W432T, M36W432B

20/57

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended. When the Program

Suspend Status bit is High (set to ‘1’), a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command. The Program Suspend Status

should only be considered valid when the Pro-

gram/Erase Controller Status bit is High (Program/

Erase Controller inactive). Bit 2 is set within 5µs of

the Program/Erase Suspend command being is-

sued therefore the memory may still complete the

operation rather than entering the Suspend mode.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Pro-

tectionStatusbitcanbeusedtoidentifyifaPro-

gram or Erase operation has tried to modify the

contents of a locked block.

When the Block Protection Status bit is High (set

to ‘1’), a Program or Erase operation has been at-

temptedonalockedblock.

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set High it should be

reset before a new command is issued, otherwise

the new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value must be masked.

Note: Refer to Appendix C, Flowcharts and

Pseudo Codes, for using the Status Register.

Table 10. Status Register Bits

Note: Logic level '1' is High, '0' is Low.

SRAM Operations

There are five standard operations that control the

SRAM component. These are Bus Read, Bus

Write, Standby/Power-down, Data Retention and

Output Disable. A summary is shown in Table 2,

Main Operation Modes

Read. Read operations are used to output the

contents of the SRAM Array. The SRAM is in Read

mode whenever Write Enable, WS

,isatV

,Out-

put Enable, GS

,isatV

, Chip Enable, E1S,isat

, Chip Enable, E2S, is at V

, and Byte Enables,

UBS

and LBS are at V

Valid data will be available on the output pins after

atimeoft

AVQV

after the last stable address. If the

Chip Enable or Output Enable access times are

not met, data access will be measured from the

limiting parameter (t

E1LQV

E2HQV

,ort

GLQV

) rath-

er than the address. Data out may be indetermi-

nate at t

E1LQX

E2HQX

and t

GLQX

, but data lines

will always be valid at t

AVQV

(see Table 19, Figures

13 and 14).

Bit Name Logic Level Definition

7 P/E.C. Status

'1' Ready

'0' Busy

6 Erase Suspend Status

'1' Suspended

'0' In progress or Completed

5 Erase Status

'1' Erase Error

'0' Erase Success

4 Program Status

'1' Program Error

'0' Program Success

PPF

Status

'1'

PPF

Invalid, Abort

'0'

PPF

2 Program Suspend Status

'1' Suspended

'0' In Progress or Completed

1 Block Protection Status

'1' Program/Erase on protected block, Abort

'0' No operation to protected blocks

0 Reserved

21/57

M36W432T, M36W432B

Write. Write operations are used to write data to

the SRAM. The SRAM is in Write mode whenever

and E1S are at V

,andE2SisatV

. Either

the Chip Enable inputs, E1S

and E2S, or the Write

Enable input, WS

, must be deasserted during ad-

dress transitions for subsequent write cycles.

A Write operation is initiated when E1S

is at V

E2S is at V

and WS is at V

. The data is latched

on the falling edge of E1S

, the rising edge of E2S

or the falling edge of WS

, whichever occurs last.

The Write cycle is terminated on the rising edge of

E1S

, the rising edge of WS or the falling edge of

E2S, whichever occurs first.

If the Output is enabled (E1S

,E2S=V

and

), then WS will return the outputs to high

impedance within t

WLQZ

of its falling edge. Care

must be taken to avoid bus contention in this type

of operation. The Data input must be valid for t

D-

VWH

before the rising edge of Write Enable, for

DVE1H

before the rising edge of E1S or for t

DVE2L

before the falling edge of E2S, whichever occurs

first, and remain valid for t

WHDX

E1HAX

or t

E2LAX

(see Table 20, Figure 16, 17, 18 and 19).

Standby/Power-Down. The SRAM component

has a chip enabled power-down feature which in-

vokes an automatic standby mode (see Table 19,

Figure 15). The SRAM is in Standby mode when-

ever either Chip Enable is deasserted, E1S

at V

or E2S at V

Data Retention. The SRAM data retention per-

formances as V

DDS

goes down to V

are de-

scribedinTable21andFigure20,21.InE1S

controlled data retention mode, the minimum

standby current mode is entered when

E1S

≥ V

DDS

– 0.2V and E2S ≤ 0.2V or

E2S ≥ V

DDS

– 0.2V. In E2S controlled data reten-

tion mode, minimum standby current mode is en-

tered when E2S ≤ 0.2V.

Output Disable. The data outputs are high im-

pedance when the Output Enable, GS

,isatV

with Write Enable, WS,atV

MAXIMUM RATING

Stressingthedeviceabovetheratinglistedinthe

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 11. Absolute Maximum Ratings

Note: 1. Depends on range.

Symbol Parameter

Value

Unit

Min Max

Ambient Operating Temperature

(1)

–40 85 °C

BIAS

Temperature Under Bias –40 125 °C

STG

Storage Temperature –55 155 °C

Input or Output Voltage –0.5

DDQF

+0.3

DDF

DDQF

Flash Supply Voltage –0.6 3.9 V

PPF

Program Voltage –0.6 13 V

DDS

SRAM Supply Voltage –0.5 3.9 V

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57

M36W432T85ZA6T

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NOR Flash 32M (2Mx16) 85ns

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