ADuCM362/ADuCM363 Data Sheet
Rev. 0| Page 10 of 24
Parameter Test Conditions/Comments Min Typ Max Unit
POWER REQUIREMENTS
Power Supply Voltages, V
DD
AVDD, IOVDD 1.8 3.6 V
Power Consumption
I
DD
(MCU Active Mode)
16, 17
Processor clock rate = 16 MHz;
all peripherals on (CLKSYSDIV = 0)
5.5 mA
Processor clock rate = 8 MHz;
all peripherals on (CLKSYSDIV = 1)
3 mA
Processor clock rate = 500 kHz; both
ADCs on (input buffers off) with PGA
gain = 4, 1 × SPI port on, all timers on
1 mA
I
DD
(MCU Powered Down)
Full temperature range, total halt mode
(Mode 4)
4 A
I
DD
, Total (ADC0)
17
PGA enabled, gain ≥ 32 320 A
PGA Gain = 4, 8, or 16, PGA only 130 A
Gain = 32, 64, or 128, PGA only 180 A
Input Buffers 2 × input buffers = 70 A 70 A
Digital Interface and Modulator 70 A
I
DD
(ADC1) Input buffers off, gain = 4, 8, or 16 only 200 A
External Reference Input Buffers 60 A each 120 A
1
These numbers are not production tested, but are guaranteed by design and/or characterization data at production release.
2
Tested at gain = 4 after initial offset calibration.
3
Measured with an internal short. A system zero-scale calibration removes this error.
4
A recalibration at any temperature removes these errors.
5
The long term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
6
These numbers do not include internal reference temperature drift.
7
Factory calibrated at gain = 1.
8
System calibration at a specific gain removes the error at this gain.
9
Input current is measured with one ADC measuring a channel. If both ADCs measure the same input channel, the input current increases (approximately doubles).
10
Measured using the box method.
11
Reference DAC linearity is calculated using a reduced code range of 0x0AB to 0xF30.
12
Measured using a low-pass filter with R = 1 kΩ, C = 100 nF.
13
Endurance is qualified to 10,000 cycles as per JEDEC Standard 22, Method A117, and is measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
14
Retention lifetime equivalent at junction temperature (T
J
) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime derates with junction temperature.
15
Voltage input levels are relevant only if driving XTAL input from a voltage source. If a crystal is connected directly, the internal crystal interface determines the
common-mode voltage.
16
Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA.
17
Total I
DD
for ADC includes figures for PGA ≥ 32, input buffers, digital interface, and the Σ-∆ modulator.
