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ADUCM362BCPZ128RL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
Data Sheet ADuCM362/ADuCM363
Rev. 0 | Page 13 of 24
External Reference (2.5 V)
Table 6 through Table 9 provide rms noise specifications for ADC0 and ADC1 using the external reference (2.5 V). Table 6 and Table 7 list
the rms noise for both ADCs with various gain and output update rate values. Table 8 and Table 9 list the typical output rms noise effective
ENOB in normal mode for both ADCs with various gain and output update rate values. (Peak-to-peak ENOB is shown in parentheses.)
Table 6. RMS Noise vs. Gain and Output Update Rate, External Reference (2.5 V), Gain = 1, 2, 4, 8, and 16
Update
Rate (Hz)
Chop/Sinc
ADCFLT
Register
Value
RMS Noise (μV)
Gain = 1, ±V
REF
,
ADCxMDE =
0x01
Gain = 2,
±500 mV,
ADCxMDE =
0x11
Gain = 4,
±250 mV,
ADCxMDE =
0x21
Gain = 8,
±125 mV,
ADCxMDE =
0x31
Gain = 16,
±62.5 mV,
ADCxMDE =
0x41
3.53 On/sinc3 0x8E7C 1.1 0.5 0.27 0.17 0.088
30 Off/sinc3 0x007E 3 1.4 0.85 0.44 0.27
50 Off/sinc3 0x007D 3.9 2.2 0.92 0.46 0.3
100 Off/sinc3 0x004D 5.2 2.8 1.25 0.63 0.38
488 Off/sinc4 0x100F 9.3 5.0 2.5 1.2 0.75
976 Off/sinc4 0x1007 12.5 7 3.5 1.75 1.2
1953 Off/sinc4 0x1003 20.0 10 5.7 2.6 1.71
3906 Off/sinc4 0x1001 140.0 70.0 35.0 17.2 8.9
Table 7. RMS Noise vs. Gain and Output Update Rate, External Reference (2.5 V), Gain = 32, 64, and 128
Update
Rate (Hz)
Chop/
Sinc
RMS Noise (μV)
ADCFLT
Register
Value
Gain = 32,
1
±62.5 mV,
ADCxMDE =
0x49
Gain = 32,
1, 2
±22.18 mV,
ADCxMDE =
0x51
Gain = 64,
3
±15.625 mV,
ADCxMDE =
0x59
Gain = 64,
3, 4
±10.3125 mV,
ADCxMDE =
0x61
Gain = 128,
5
±7.8125 mV,
ADCxMDE =
0x69
Gain = 128,
5, 6
±3.98 mV,
ADCxMDE =
0x71
3.53 On/sinc3 0x8E7C 0.076 0.07 0.088 0.06 0.068 0.58
30 Off/sinc3 0x007E 0.21 0.22 0.21 0.19 0.175 0.17
50 Off/sinc3 0x007D 0.265 0.21 0.27 0.2 0.225 0.19
100 Off/sinc3 0x004D 0.37 0.32 0.366 0.28 0.32 0.26
488 Off/sinc4 0x100F 0.73 0.7 0.73 0.57 0.64 0.5
976 Off/sinc4 0x1007 1.1 0.83 1.01 0.77 0.89 0.75
1953 Off/sinc4 0x1003 2.05 1.3 1.6 1.24 1.3 1.1
3906 Off/sinc4 0x1001 9.4 4.8 5.1 2.65 3.2 1.88
1
ADCxMDE = 0x49 sets the PGA for a gain of 16 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x51 sets the PGA for a gain of 32 with the modulator gain off. ADCxMDE = 0x49 has slightly higher noise but supports a wider input range.
2
If AVDD < 2.0 V and ADCxMDE = 0x51, the input range is ±17.5 mV.
3
ADCxMDE = 0x59 sets the PGA for a gain of 32 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x61 sets the PGA for a gain of 64 with the modulator gain off. ADCxMDE = 0x59 has slightly higher noise but supports a wider input range.
4
If AVDD < 2.0 V and ADCxMDE = 0x61, the input range is ±8.715 mV.
5
ADCxMDE = 0x69 sets the PGA for a gain of 64 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x71 sets the PGA for a gain of 128 with the modulator gain off. ADCxMDE = 0x69 has slightly higher noise but supports a wider input range.
6
If AVDD < 2.0 V and ADCxMDE = 0x71, the input range is ±3.828 mV.
ADuCM362/ADuCM363 Data Sheet
Rev. 0| Page 14 of 24
Table 8. Typical Output RMS Noise ENOB in Normal Mode, External Reference (2.5 V), Gain = 1, 2, 4, 8, and 16
Update
Rate (Hz) Chop/Sinc
ENOB by Input Voltage Range and Gain
1
Gain = 1, ±V
REF
,
ADCxMDE = 0x01
Gain = 2, ±500 mV,
ADCxMDE = 0x11
Gain = 4, ±250 mV,
ADCxMDE = 0x21
Gain = 8, ±125 mV,
ADCxMDE = 0x31
Gain = 16,
±62.5 mV,
ADCxMDE = 0x41
3.53 On/sinc3 22.1 (19.4 p-p) 20.9 (18.2 p-p) 20.8 (18.1 p-p) 20.5 (17.7 p-p) 20.43 (17.7 p-p)
30 Off/sinc3 20.7 (18.0 p-p) 19.4 (16.7 p-p) 19.2 (16.4 p-p) 19.1 (16.4 p-p) 18.82 (16.1 p-p)
50 Off/sinc3 20.3 (17.6 p-p) 18.8 (16.1 p-p) 19.05 (16.3 p-p) 19.05 (16.3 p-p) 18.66 (15.9 p-p)
100 Off/sinc3 19.9 (17.2 p-p) 18.4 (15.7 p-p) 18.6 (15.9 p-p) 18.6 (15.9 p-p) 18.32 (15.6 p-p)
488 Off/sinc4 19.0 (16.3 p-p) 17.6 (14.9 p-p) 17.6 (14.9 p-p) 17.7 (14.9 p-p) 17.34 (14.6 p-p)
976 Off/sinc4 18.6 (15.9 p-p) 17.1 (14.4 p-p) 17.1 (14.4 p-p) 17.1 (14.4 p-p) 16.66 (13.9 p-p)
1953 Off/sinc4 17.9 (15.2 p-p) 16.6 (13.9 p-p) 16.4 (13.7 p-p) 16.55 (13.8 p-p) 16.15 (13.4 p-p)
3906 Off/sinc4 15.1 (12.4 p-p) 13.8 (11.1 p-p) 13.8 (11.1 p-p) 13.8 (11.1 p-p) 13.77 (11.05 p-p)
1
RMS bits are calculated as follows: log
2
((2 × Input Range)/RMS Noise); peak-to-peak (p-p) bits are calculated as follows: log
2
((2 × Input Range)/(6.6 × RMS Noise)).
Table 9. Typical Output RMS Noise ENOB in Normal Mode, External Reference (2.5 V), Gain = 32, 64, and 128
Update
Rate (Hz) Chop/Sinc
ENOB by Input Voltage Range and Gain
1
Gain = 32,
±62.5 mV,
ADCxMDE =
0x49
Gain = 32,
±22.18 mV,
ADCxMDE =
0x51
Gain = 64,
±15.625 mV,
ADCxMDE =
0x59
Gain = 64,
±10.3125 mV,
ADCxMDE =
0x61
Gain = 128,
±7.8125 mV,
ADCxMDE =
0x69
Gain = 128,
±3.98 mV,
ADCxMDE =
0x71
3.53 On/sinc3 19.6 (16.9 p-p) 19.3 (16.55 p-p) 18.4 (15.7 p-p) 18.4 (15.7 p-p) 17.8 (15.1 p-p) 17.1 (14.3 p-p)
30 Off/sinc3 18.2 (15.5 p-p) 17.6 (14.9 p-p) 17.2 (14.5 p-p) 16.7 (14.0 p-p) 16.4 (13.7 p-p) 15.5 (12.8 p-p)
50 Off/sinc3 17.8 (15.1 p-p) 17.7 (15.0 p-p) 16.8 (14.1 p-p) 16.65 (13.9 p-p) 16.1 (13.4 p-p) 15.35 (12.6 p-p)
100 Off/sinc3 17.4 (14.6 p-p) 17.1 (14.35 p-p) 16.4 (13.7 p-p) 16.2 (13.4 p-p) 15.6 (12.85 p-p) 14.9 (12.2 p-p)
488 Off/sinc4 16.4 (13.7 p-p) 16.0 (13.2 p-p) 15.4 (12.7 p-p) 15.1 (12.4 p-p) 14.6 (11.85 p-p) 14.0 (11.2 p-p)
976 Off/sinc4 15.8 (13.1 p-p) 15.7 (13.0 p-p) 14.9 (12.2 p-p) 14.7 (12.0 p-p) 14.1 (11.4 p-p) 13.4 (10.6 p-p)
1953 Off/sinc4 14.9 (12.1 p-p) 15.1 (12.3 p-p) 14.25 (11.5 p-p) 14.0 (11.3 p-p) 13.55 (10.8 p-p) 12.8 (10.1 p-p)
3906 Off/sinc4 12.7 (10.0 p-p) 13.2 (10.4 p-p) 12.6 (9.9 p-p) 12.9 (10.2 p-p) 12.25 (9.5 p-p) 12.0 (9.3 p-p)
1
RMS bits are calculated as follows: log
2
((2 × Input Range)/RMS Noise); peak-to-peak (p-p) bits are calculated as follows: log
2
((2 × Input Range)/(6.6 × RMS Noise)).
Data Sheet ADuCM362/ADuCM363
Rev. 0 | Page 15 of 24
I
2
C TIMING SPECIFICATIONS
The capacitive load for each I
2
C bus line (C
B
) is 400 pF maximum as per the I
2
C bus specifications. I
2
C timing is guaranteed by design, but
is not production tested.
Table 10. I
2
C Timing in Fast Mode (400 kHz)
Parameter Description Min Max Unit
t
L
Serial clock (SCL) low pulse width 1300 ns
t
H
SCL high pulse width 600 ns
t
SHD
Start condition hold time 600 ns
t
DSU
Data setup time 100 ns
t
DHD
Data hold time 0 ns
t
RSU
Setup time for repeated start 600 ns
t
PSU
Stop condition setup time 600 ns
t
BUF
Bus free time between a stop condition and a start condition 1.3
s
t
R
Rise time for both SCL and serial data (SDA) 20 + 0.1 C
B
300 ns
t
F
Fall time for both SCL and SDA 20 + 0.1 C
B
300 ns
t
SUP
Pulse width of suppressed spike 0 50 ns
Table 11. I
2
C Timing in Standard Mode (100 kHz)
Parameter Description Min Max Unit
t
L
SCL low pulse width 4.7 s
t
H
SCL high pulse width 4.0 ns
t
SHD
Start condition hold time 4.7 s
t
DSU
Data setup time 250 ns
t
DHD
Data hold time 0 s
t
RSU
Setup time for repeated start 4.0 s
t
PSU
Stop condition setup time 4.0 s
t
BUF
Bus free time between a stop condition and a start condition 4.7 s
t
R
Rise time for both SCL and SDA 1 s
t
F
Fall time for both SCL and SDA 300 ns
SDA (I/O)
t
BUF
MSB LSB ACK MSB
1981
SCL (I)
PS
STOP
CONDITION
START
CONDITION
S(R)
REPEATED
START
t
SUP
t
R
t
F
t
F
t
R
t
H
t
L
t
SUP
t
DSU
t
DHD
t
RSU
t
DHD
t
DSU
t
SHD
t
PSU
14919-002
Figure 3. I
2
C-Compatible Interface Timing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

ADUCM362BCPZ128RL7

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Analog Devices Inc.
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ARM Microcontrollers - MCU Cortex M3 + 16K/128K + Dual 24bit SD AFE
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