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ADUCM362BCPZ128RL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
ADuCM362/ADuCM363 Data Sheet
Rev. 0| Page 22 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
60
50
40
30
20
INPUT CURRENT (nA)
10
0
–10
0.5 1.0 1.5
COMMON-MODE VOLTAGE (V)
2.0 2.5 3.0 3.50
–20
–30
I
P
I
P
– I
N
I
N
14919-008
Figure 9. Input Current vs. Common-Mode Voltage (V
CM
), Gain = 4,
ADC Input = 250 mV, AVDD = 3.6 V, T
A
= 25°C, V
CM
= ((AIN+) + (AIN−))/2
5
4
3
2
1
0
INPUT CURRENT (nA)
–1
–2
–3
0.5 1.0 1.5
COMMON-MODE VOLTAGE (V)
2.0 2.5 3.0 3.50
–4
–5
I
P
I
P
– I
N
I
N
14919-009
Figure 10. Input Current vs. Common-Mode Voltage (V
CM
), Gain = 128,
ADC Input = 7.8125 mV, AVDD = 3.6 V, T
A
= 25°C, V
CM
= ((AIN+) + (AIN−))/2
–40 –20 0 20
14000000
12000000
10000000
8000000
6000000
4000000
2000000
40
TEMPERATURE (°C)
ADC CODES
60 80 100 120
14919-010
Figure 11. ADC Codes (Decimal Values) vs. Die Temperature
0
50
100
150
200
250
0 200 400 600 800 1000 1200
SETTLING TIME (ms)
CAPACITANCE (nF)
BOOST = 0
BOOST = 30
14919-011
Figure 12. VBIASx Output Settling Time vs. Load Capacitance, T
A
= 25°C,
IOVDD and AVDD = 3.3 V
0
5
10
15
20
25
30
0 0.51.01.52.02.53.03.5
PULL-UP RESI
S
TANCE (kΩ)
VOLTAGE (V)
14919-012
Figure 13. Digital Input Pin Pull-Up Resistance Value vs. Voltage Applied
to Digital Pin, T
A
= 25°C, IOVDD = 3.4 V
0
10
20
30
40
50
60
0 0.5 1.0 1.5 2.0
PULL-UP RESI
S
TANCE (kΩ)
VOLTAGE (V)
14919-013
Figure 14. Digital Input Pin Pull-Up Resistance Value vs. Voltage Applied
to Digital Pin, T
A
= 25°C, IOVDD = 1.8 V
Data Sheet ADuCM362/ADuCM363
Rev. 0 | Page 23 of 24
TYPICAL SYSTEM CONFIGURATION
Figure 15 shows a typical ADuCM362/ADuCM363 configuration.
This figure illustrates some of the hardware considerations. The
bottom of the LFCSP package has an exposed pad that must be
soldered to a metal plate on the PCB for mechanical reasons
and to DGND. The metal plate of the PCB can be connected to
ground. Place the 0.47 µF capacitor on the AVDD_REG and
DVDD_REG pins as close to the pins as possible. In noisy
environments, an additional 1 nF capacitor can be added to
IOVDD and AVDD.
1
2
3
P0.7/POR/TxD1
P0.6/IRQ2/RxD1
P0.5/CTS/IRQ1
4
P0.4/RTS/ECLKO/RTS1
5
P0.3/IRQ0/CS1/RTS1/RTS
6
P0.2/MOSI1/SDA/TxD
7
P0.1/SCLK1/SCL/RxD
24
AIN7/VBIAS0/
IEXC/
EXTREF2IN+
23
AIN6/IEXC
22
AIN5/IEXC
21
IREF
20
INT_REF
19
DAC
18
AVDD_REG
17
AVDD
16
AGND
12pF
12pF
15
VREF–
14
VREF+
13
GND
_SW
44
P1.6/IRQ6/
PW
M4/MOSI0
45
P1.7/IRQ7
/
PW
M5/CS0
46
P2.0/SCL/
UARTCLK
47
SW
CLK
48
SW
D
IO
SW
CLK
SW
DIO
43
P1.5/IRQ5/
PW
M3/SCLK0
42
P1.4/PW
M2/
MISO0
41
P1.3/PW
M1/
DSR
40
P1.2
/PW
M0/RI
39
P1.1/IRQ4/PW
MTRIP/DTR
38
P1.0/IRQ3/PW
M
SYNC/EXTCLK
37
IOVDD
ADuCM362/
ADuCM363
25
AIN4/IEXC
26
AIN3
27
AIN2
28
AIN1
29
AIN0
30
DVDD_REG
DVDD
DGND
31
IOVDD
32
XTALI
33
XTALO
34
P2.2/BM
35
P2.1/SDA/UART1DCD/UARTDCD
36
RESET
RESET
RESET
RESET
8
P0.0/MISO1/UART1DCD/UARTDCD
9
AIN11/VBIAS1
10
AIN10
11
AIN9/DACBUFF+
12
AIN8/EXTREF2IN–
0.47µF
0.47µF
0.
1µF
15
0kΩ
GND
DGND
SW
IO
TX
SW
CLK
RX
5V USB
SW
DIO
INTERFACE BOARD CONNECTOR
SW
CLK
DVDD
DGND
DGND
0.1µF
AVDD
0.47µF
0.1µF
0.1µF
1µ
F
0.1µF
560Ω
1.6Ω
IN
OUT
E
N
GND
D
GND
DGND
DGND
AVDDDVDD
AGND AGND AGND
4.7µF
4.7µF
ADP1720ARMZ-3.3
DGND
14919-115
Figure 15. Typical System Configuration
ADuCM362/ADuCM363 Data Sheet
Rev. 0| Page 24 of 24
OUTLINE DIMENSIONS
112408-B
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.
1
0.50
BSC
BOTTOM VIEW
TOP VIEW
PIN 1
INDI
C
ATOR
7.00
BSC SQ
48
13
24
25
36
37
12
EXPOSED
PAD
P
I
N
1
I
N
D
I
C
A
T
O
R
5.20
5.10 SQ
5.00
0.45
0.40
0.35
S
EATING
PLANE
0.80
0.75
0.70
0.05 MAX
0.02 NOM
0.25 MIN
0.20 REF
COPLANARITY
0.08
0.30
0.23
0.18
Figure 16. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
ADCs Flash/SRAM Temperature Range Package Description
Package
Option
Ordering
Quantity
ADuCM362BCPZ256 Dual 24-Bit 256 kB/24 kB −40°C to +125°C 48-Lead LFCSP CP-48-4
ADuCM362BCPZ256RL7 Dual 24-Bit 256 kB/24 kB −40°C to +125°C 48-Lead LFCSP CP-48-4 750
ADuCM362BCPZ128 Dual 24-Bit 128 kB/16 kB −40°C to +125°C 48-Lead LFCSP CP-48-4
ADuCM362BCPZ128RL7 Dual 24-Bit 128 kB/16 kB −40°C to +125°C 48-Lead LFCSP CP-48-4 750
ADuCM363BCPZ256 Single 24-Bit 256 kB/24 kB −40°C to +125°C 48-Lead LFCSP CP-48-4
ADuCM363BCPZ256RL7 Single 24-Bit 256 kB/24 kB −40°C to +125°C 48-Lead LFCSP CP-48-4 750
ADuCM363BCPZ128 Single 24-Bit 128 kB/16 kB −40°C to +125°C 48-Lead LFCSP CP-48-4
ADuCM363BCPZ128RL7 Single 24-Bit 128 kB/16 kB −40°C to +125°C 48-Lead LFCSP CP-48-4 750
EVAL-ADuCM362QSPZ
ADuCM362 QuickStart Plus
Development System
EVAL-ADuCM363QSPZ
ADuCM363 QuickStart Plus
Development System
1
Z = RoHS Compliant Part.
I
2
C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14919-0-10/16(0)
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ADUCM362BCPZ128RL7

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Buy ADUCM362BCPZ128RL7
Manufacturer:
Analog Devices Inc.
Description:
ARM Microcontrollers - MCU Cortex M3 + 16K/128K + Dual 24bit SD AFE
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