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ADUCM362BCPZ128RL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
ADuCM362/ADuCM363 Data Sheet
Rev. 0| Page 16 of 24
SPI TIMING SPECIFICATIONS
Table 12. SPI Master Mode Timing
Parameter Description Min Typ Max Unit
t
SL
SCLK low pulse width
1
(SPIDIV + 1) × t
UCLK
ns
t
SH
SCLK high pulse width
1
(SPIDIV + 1) × t
UCLK
ns
t
DAV
Data output valid after SCLK edge 0 35.5 ns
t
DOSU
Data output setup time before SCLK edge
1
(SPIDIV + 1) × t
UCLK
ns
t
DSU
Data input setup time before SCLK edge 58.7 ns
t
DHD
Data input hold time after SCLK edge 16 ns
t
DF
Data output fall time 12 35.5 ns
t
DR
Data output rise time 12 35.5 ns
t
SR
SCLK rise time 12 35.5 ns
t
SF
SCLK fall time 12 35.5 ns
1
t
UCLK
= 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider.
SCLK
(POLARITY = 0)
CS
1/2 SCLK
CYCLE
SCLK
(POLARITY = 1)
MOSI MSB BIT 6 TO BIT 1 LSB
MISO MSB IN BIT 6 TO BIT 1 LSB IN
t
SH
t
CS
t
SL
3/4 SCLK
CYCLE
t
SFS
t
SR
t
SF
t
DR
t
DF
t
DAV
t
DSU
t
DHD
14919-003
Figure 4. SPI Master Mode Timing (Phase Mode = 1)
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
MOSI MSB BIT 6 TO BIT 1 LSB
MISO MSB IN BIT 6 TO BIT 1 LSB IN
t
SH
t
SR
t
SF
t
DR
t
DF
t
DAV
t
DOSU
t
DSU
t
DHD
CS
1 SCLK CYCLE
t
CS
t
SL
1 SCLK CYCLE
t
SFS
14919-004
Figure 5. SPI Master Mode Timing (Phase Mode = 0)
Data Sheet ADuCM362/ADuCM363
Rev. 0 | Page 17 of 24
Table 13. SPI Slave Mode Timing
Parameter Description Min Typ Max Unit
t
CS
CS
to SCLK edge
62.5 ns
t
SL
SCLK low pulse width
1
(SPIDIV + 1) × t
UCLK
ns
t
SH
SCLK high pulse width
1
62.5 (SPIDIV + 1) × t
UCLK
ns
t
DAV
Data output valid after SCLK edge 49.1 ns
t
DSU
Data input setup time before SCLK edge 20.2 ns
t
DHD
Data input hold time after SCLK edge 10.1 ns
t
DF
Data output fall time 12 35.5 ns
t
DR
Data output rise time 12 35.5 ns
t
SR
SCLK rise time 12 35.5 ns
t
SF
SCLK fall time 12 35.5 ns
t
SFS
CS
high after SCLK edge
0 ns
1
t
UCLK
= 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider.
SCLK
(POLARITY = 0)
CS
SCLK
(POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
t
SFS
MISO MSB BIT 6 TO BIT 1 LSB
MOSI MSB IN BIT 6 TO BIT 1 LSB IN
t
DHD
t
DSU
t
DAV
t
DR
t
DF
t
CS
14919-005
Figure 6. SPI Slave Mode Timing (Phase Mode = 1)
SCLK
(POLARITY = 0)
CS
SCLK
(POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
t
SFS
MISO
MSB BIT 6 TO BIT 1 LSB
MOSI MSB IN BIT 6 TO BIT 1 LSB IN
t
DHD
t
DSU
t
DAV
t
DR
t
DF
t
DOCS
t
CS
14919-006
Figure 7. SPI Slave Mode Timing (Phase Mode = 0)
ADuCM362/ADuCM363 Data Sheet
Rev. 0| Page 18 of 24
ABSOLUTE MAXIMUM RATINGS
Table 14.
Parameter Rating
AVDD to AGND −0.3 V to +3.96 V
IOVDD to DGND −0.3 V to +3.96 V
Digital Input Voltage to DGND −0.3 V to +3.96 V
Digital Output Voltage to DGND −0.3 V to +3.96 V
Analog Inputs to AGND −0.3 V to +3.96 V
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
ESD Rating, All Pins
Human Body Model (HBM) ±2 kV
Field-Induced Charged Device
Model (FICDM)
±850 V
Peak Solder Reflow Temperature
SnPb Assemblies (10 sec to 30 sec) 240°C
Pb-Free Assemblies (20 sec to 40 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
Table 15. Thermal Resistance
Package Type θ
JA
Unit
CP-48-4 27 °C/W
ESD CAUTION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

ADUCM362BCPZ128RL7

Mfr. #:
Buy ADUCM362BCPZ128RL7
Manufacturer:
Analog Devices Inc.
Description:
ARM Microcontrollers - MCU Cortex M3 + 16K/128K + Dual 24bit SD AFE
Lifecycle:
New from this manufacturer.
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