ZL30120 Data Sheet
11
Zarlink Semiconductor Inc.
1.0 Functional Description
The ZL30120 Multi-Rate Line Card Synchronizer is a highly integrated device that provides timing and
synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one
of eight input references and provides a wide variety of synchronized output clocks and frame pulses.
1.1 DPLL Features
The ZL30120 provides two independently controlled Digital Phase-Locked Loops (DPLL1, DPLL2) for clock and/or
frame pulse synchronization. DPLL1 is the main DPLL and is always enabled. To save on power, DPLL2 is disabled
by default. For applications where DPLL2 is required, it must be enabled using the dpll_en bit of the dpll2_ctrl_0
register (0x2A). Table 1 shows a feature summary for both DPLLs.
Feature DPLL1 DPLL2
Modes of Operation Free-run, Normal (locked), Holdover Free-run, Normal (locked), Holdover
Loop Bandwidth User selectable: 14 Hz, 28 Hz, or
wideband
1
(890 Hz / 56 Hz / 14 Hz)
1. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies equal to or
greater than 64 kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to or greater than 8 kHz and less than 64 kHz, the
loop bandwidth = 56 Hz. For reference frequencies equal to 2 kHz, the loop bandwidth is equal to 14 Hz.
Fixed: 14 Hz
Phase Slope Limiting User selectable: 885 ns/s, 7.5 µs/s,
61 µs/s, or unlimited
User selectable: 61 µs/s, or unlimited
Pull-in Range Fixed: 130 ppm Fixed: 130 ppm
Holdover Parameters Selectable Update Times: 26 ms, 1 s,
10 s, 60 s, and Selectable Holdover
Post Filter BW: 18 mHz, 2.5 Hz, 10 Hz.
Fixed Update Time: 26 ms
No Holdover Post Filtering
Holdover Frequency
Accuracy
Better than 1 ppb (Stratum 3E) initial
frequency offset. Frequency drift
depends on the 20 MHz external
oscillator.
Better than 50 ppb (Stratum 3) initial
frequency offset. Frequency drift
depends on the 20 MHz external
oscillator.
Reference Inputs Ref0 to Ref7 Ref0 to Ref7
Sync Inputs Sync0, Sync1, Sync2 Sync inputs are not supported.
Input Reference
Selection/Switching
Automatic (based on programmable
priority and revertiveness), or manual
Automatic (based on programmable
priority and revertiveness), or manual
Hitless Ref Switching Can be enabled or disabled Can be enabled or disabled
Output Clocks apll_clk0, apll_clk1, p0_clk0, p0_clk1,
p1_clk0, p1_clk1, fb_clk.
p0_clk0, p0_clk1, p1_clk0, p1_clk1.
Output Frame Pulses apll_fp0, apll_fp1, p0_fp0, p0_fp1
synchronized to active sync reference.
p0_fp0, p0_fp1 not synchronized to sync
reference.
External Pins Status
Indicators
Lock, Holdover None
Table 1 - DPLL1 and DPLL2 Features
