ZL30120 Data Sheet
7
Zarlink Semiconductor Inc.
J10 p1_clk0 O Programmable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 100 MHz in
addition to 2 kHz. The default frequency for this output is 1.544 MHz (DS1).
K10 p1_clk1 O Programmable Synthesizer1 - Output Clock 1 (LVCMOS). This is a
programmable clock output configurable as a multiple or division of the p1_clk0
frequency within the range of 2 kHz to 100 MHz. The default frequency for this
output is 3.088 MHz (2x DS1).
H10 fb_clk O Feedback Clock (LVCMOS). This output is a buffered copy of the feedback
clock for DPLL1. The frequency of this output always equals the frequency of the
selected reference.
E1 dpll2_ref O DPLL2 Selected Output Reference (LVCMOS). This is a buffered copy of the
output of the reference selector for DPLL2. Switching between input reference
clocks at this output is not hitless.
Control
H5 rst_b I Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To
ensure proper operation, the device must be reset after power-up. Reset should
be asserted for a minimum of 300 ns.
J5 dpll1_hs_en I
u
DPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high at
this input enables hitless reference switching. A logic low disables hitless
reference switching and re-aligns DPLL1’s output phase to the phase of the
selected reference input. This feature can also be controlled through software
registers. This pin is internally pulled up to Vdd.
C2
D2
dpll1_mod_sel0
dpll1_mod_sel1
I
u
DPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the levels
on these pins determine the default mode of operation for DPLL1 (Automatic,
Normal, Holdover or Freerun). After reset, the mode of operation can be
controlled directly with these pins, or by accessing the dpll1_modesel register
through the serial interface. This pin is internally pulled up to Vdd.
Status
H1 dpll1_lock O Lock Indicator (LVCMOS). This is the lock indicator pin for DPLL1. This output
goes high when DPLL1’s output is frequency and phase locked to the input
reference.
J1 dpll1_holdover O Holdover Indicator (LVCMOS). This pin goes high when DPLL1 enters the
holdover mode.
Serial Interface
E2 sck I Clock for Serial Interface (LVCMOS). Serial interface clock.
F1 si I Serial Interface Input (LVCMOS). Serial interface data input pin.
G1 so O Serial Interface Output (LVCMOS). Serial interface data output pin.
E3 cs_b I
u
Chip Select for Serial Interface (LVCMOS). Serial interface chip select. This
pin is internally pulled up to Vdd.
Pin # Name
I/O
Type
Description
