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ZL30120GGG2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
ZL30120 Data Sheet
22
Zarlink Semiconductor Inc.
42 p0_fp0_offset_2 00 Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
43 p0_fp1_freq 05 Control register to select p0_fp1 frame pulse
frequency
R/W
44 p0_fp1_type 11 Control register to select fp1 type R/W
45 p0_fp1_offset_0 00 Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/262.144 MHz
R/W
46 p0_fp1_offset_1 00 Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.144 MHz
R/W
47 p0_fp1_offset_2 00 Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
P1 Configuration Registers
48 p1_enable 83 Control register to enable p1_clk0, p1_clk1, the
P1 synthesizer and select the source
R/W
49 p1_run 03 Control register to generate enable/disable
p1_clk0 and p1_clk1
R/W
4A p1_freq_0 C1 Control register for the [7:0] bits of the N of
N*8k clk0
R/W
4B p1_freq_1 00 Control register for the [13:8] bits of the N of
N*8k clk0
R/W
4C p1_clk0_offset90 00 Control register for the p1_clk0 phase position
coarse tuning
R/W
4D p1_clk1_div 3F Control register for the p1_clk1 frequency
selection
R/W
4E p1_clk1_offset90 00 Control register for the p1_clk1 phase position
coarse tuning
R/W
4F p1_offset_fine 00 Control register for the output/output phase
alignrment fine tuning
R/W
APLL Configuration Registers
50 apll_enable 8F Control register to enable apll_clk0, apll_clk1,
apll_fp0, apll_fp1 and the APLL
R/W
51 apll_run 0F Control register to generate apll_clk0,
apll_clk1, apll_fp0 and apll_fp1
R/W
52 apll_clk_div 42 Control register for the apll_clk0 and apll_clk1
frequency selection
R/W
53 apll_clk0_offset90 00 Control register for the apll_clk0 phase position
coarse tuning
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
ZL30120 Data Sheet
23
Zarlink Semiconductor Inc.
54 apll_clk1_offset90 00 Control register for the apll_clk1 phase position
coarse tuning
R/W
55 apll_offset_fine 00 Control register for the output/output phase
alignment fine tuning for apll path
R/W
56 apll_fp0_freq 05 Control register to select the apll_fp0 frame
pulse frequency
R/W
57 apll_fp0_type 23 Control register to select fp0 type R/W
58 apll_fp0_offset_0 00 Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
59 apll_fp0_offset_1 00 Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5A apll_fp0_offset_2 00 Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
5B apll_fp1_freq 03 Control register to select apll_fp1 frame pulse
frequency
R/W
5C apll_fp1_type 03 Control register to select fp1 type R/W
5D apll_fp1_offset_0 00 Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5E apll_fp1_offset_1 00 Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5F apll_fp1_offset_2 00 Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
60 reserved A3 Leave as default R/W
61 reserved 53 Leave as default R/W
External Feedback Configuration
62 fb_control 81 Control register to enable fb_clk and the FB
PLL, int/ext feedback select
R/W
63 fb_offset_fine F5 Control register for the output/output phase
alignment fine tuning
R/W
64 reserved
N * 8 kHz Reference Control
65 ref_freq_mode_0 00 Control register to set whether to use auto
detect, CustomA or CustomB for ref0 to ref3
R/W
66 ref_freq_mode_1 00 Control register to set whether to use auto
detect, CustomA or CustomB for ref4 to ref7
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
ZL30120 Data Sheet
24
Zarlink Semiconductor Inc.
67 custA_mult_0 00 Control register for the [7:0] bits of the custom
configuration A. This is the N integer for the
N*8kHz reference monitoring.
R/W
68 custA_mult_1 00 Control register for the [13:8] bits of the custom
configuration A. This is the N integer for the
N*8kHz reference monitoring.
R/W
69 custA_scm_low 00 Control register for the custom configuration A:
single cycle SCM low limiter
R/W
6A custA_scm_high 00 Control register for the custom configuration
A: single cycle SCM high limiter
R/W
6B custA_cfm_low_0 00 Control register for the custom configuration
A: The [7:0] bits of the single cycle CFM low
limit
R/W
6C custA_cfm_low_1 00 Control register for the custom configuration
A: The [15:0] bits of the single cycle CFM low
limit
R/W
6D custA_cfm_hi_0 00 Control register for the custom configuration
A: The [7:0] bits of the single cycle CFM high
limit
R/W
6E custA_cfm_hi_1 00 Control register for the custom configuration
A: The [15:0] bits of the single cycle CFM high
limiter
R/W
6F custA_cfm_cycle 00 Control register for the custom configuration
A: CFM reference monitoring cycles - 1
R/W
70 custA_div 00 Control register for the custom configuration
A: enable the use of ref_div4 for the CFM and
PFM inputs
R/W
71 custB_mult_0 00 Control register for the [7:0] bits of the custom
configuration B. This is the 8 k integer for the
N*8kHz reference monitoring.
R/W
72 custB_mult_1 00 Control register for the [13:8] bits of the custom
configuration B. This is the 8 k integer for the
N*8kHz reference monitoring.
R/W
73 custB_scm_low 00 Control register for the custom configuration B:
single cycle SCM low limiter
R/W
74 custB_scm_high 00 Control register for the custom configuration
B: single cycle SCM high limiter
R/W
75 custB_cfm_low_0 00 Control register for the custom configuration
B: The [7:0] bits of the single cycle CFM low
limiter.
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

ZL30120GGG2

Mfr. #:
Buy ZL30120GGG2
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Pb Free Low Jitter Linecard Synchronizer
Lifecycle:
New from this manufacturer.
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