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ZL30120GGG2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
ZL30120 Data Sheet
19
Zarlink Semiconductor Inc.
0F ref_mon_fail_mask_3 FF Control register to mask each failure indicator
for ref6 and ref7
R/W
Reference Monitor Setup
10 detected_ref_0 FF Ref0 and ref1 auto-detected frequency value
status register
R
11 detected_ref_1 FF Ref2 and ref3 auto-detected frequency value
status register
R
12 detected_ref_2 FF Ref4 and ref5 auto-detected frequency value
status register
R
13 detected_ref_3 FF Ref6 and ref7 auto-detected frequency value
status register
R
14 detected_sync_0 EE Sync0 and sync1 auto-detected frequency
value and sync failure status register
R
15 detected_sync_1 0E Sync2 auto-detected frequency value and sync
valid status register
R
16 oor_ctrl_0 33 Control register for the ref0 and ref1 out of
range limit
R/W
17 oor_ctrl_1 33 Control register for the ref2 and ref3 out of
range limit
R/W
18 oor_ctrl_2 33 Control register for the ref4 and ref5 out of
range limit
R/W
19 oor_ctrl_3 33 Control register for the ref6 and ref7 out of
range limit
R/W
1A gst_mask_0 FF Control register to mask the inputs to the guard
soak timer for ref0 to ref3
R/W
1B gst_mask_1 FF Control register to mask the inputs to the guard
soak timer for ref4 to ref7
R/W
1C gst_qualif_time 1A Control register for the guard_soak_timer
qualification time and disqualification time for
the references
R/W
DPLL1 Control
1D dpll1_ctrl_0 See
Register
Description
Control register for the DPLL1 filter control;
phase slope limit, bandwidth and hitless
switching
R/W
1E dpll1_ctrl_1 See
Register
Description
Holdover update time, filter_out_en,
freq_offset_en, revert enable
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
ZL30120 Data Sheet
20
Zarlink Semiconductor Inc.
1F dpll1_modesel See
Register
Description
Control register for the DPLL1 mode of
operation
R/W
20 dpll1_refsel 00 DPLL1 reference selection or reference
selection status
R/W
21 dpll1_ref_fail_mask 3C Control register to mask each failure indicator
(SCM, CFM, PFM and GST) used for automatic
reference switching and automatic holdover
R/W
22 dpll1_wait_to_restore 00 Control register to indicate the time to restore a
previous failed reference
R/W
23 dpll1_ref_rev_ctrl 00 Control register for the ref0 to ref7 enable
revertive signals
R/W
24 dpll1_ref_pri_ctrl_0 10 Control register for the ref0 and ref1 priority
values
R/W
25 dpll1_ref_pri_ctrl_1 32 Control register for the ref2 and ref3 priority
values
R/W
26 dpll1_ref_pri_ctrl_2 54 Control register for the ref4 and re5 priority
values
R/W
27 dpll1_ref_pri_ctrl_3 76 Control register for the ref6 and ref7 priority
values
R/W
28 dpll1_lock_holdover_status 04 DPLL1 lock and holdover status register R
29 dpll1_pullinrange 03 Control register for the pull-in range R/W
DPLL2 Control
2A dpll2_ctrl_0 00 Control register to program the DPLL2: hitless
switching, the phase slope limit and DPLL
enable
R/W
2B dpll2_ctrl_1 04 Control register to program the DPLL2:
filter_out_en, freq_offset_en, revert enable
R/W
2C dpll2_modesel 02 Control register to select the mode of operation
of the DPLL2
R/W
2D dpll2_refsel 00 DPLL2 reference selection or reference
selection status
R/W
2E dpll2_ref_fail_mask 3C Control register to mask each failure indicator
(SCM, CFM, PFM and GST) used for automatic
reference switching and automatic holdover
R/W
2F dpll2_wait_to_restore 00 Control register to indicate the time to restore a
previous failed reference for the DPLL2 path
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
ZL30120 Data Sheet
21
Zarlink Semiconductor Inc.
30 dpll2_ref_rev_ctrl 00 Control register for the ref0 to ref7 enable
revertive signals
R/W
31 dpll2_ref_pri_ctrl_0 10 Control register for the ref0 and ref1 priority
values
R/W
32 dpll2_ref_pri_ctrl_1 32 Control register for the ref2 and ref3 priority
values
R/W
33 dpll2_ref_pri_ctrl_2 54 Control register for the ref4 and re5 priority
values
R/W
34 dpll2_ref_pri_ctrl_3 76 Control register for the ref6 and ref7 priority
values
R/W
35 dpll2_lock_holdover_status 04 DPLL2 lock and holdover status register R
P0 Configuration Registers
36 p0_enable 8F Control register to enable p0_clk0, p0_clk1,
p0_fp0, p0_fp1, the P0 synthesizer and select
the source
R/W
37 p0_run 0F Control register to generate p0_clk0, p0_clk1,
p0_fp0 and p0_fp1
R/W
38 p0_freq_0 00 Control register for the [7:0] bits of the N of
N*8k clk0
R/W
39 p0_freq_1 01 Control register for the [13:8] bits of the N of
N*8k clk0
R/W
3A p0_clk0_offset90 00 Control register for the p0_clk0 phase position
coarse tuning
R/W
3B p0_clk1_div 3E Control register for the p0_clk1 frequency
selection
R/W
3C p0_clk1_offset90 00 Control register for the p0_clk1 phase position
coarse tuning
R/W
3D p0_offset_fine 00 Control register for the output/output phase
alignment fine tuning for p0 path
R/W
3E p0_fp0_freq 05 Control register to select the p0_fp0 frame
pulse frequency
R/W
3F p0_fp0_type 83 Control register to select fp0 type R/W
40 p0_fp0_offset_0 00 Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/262.14 MHz
R/W
41 p0_fp0_offset_1 00 Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.14 MHz
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

ZL30120GGG2

Mfr. #:
Buy ZL30120GGG2
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Pb Free Low Jitter Linecard Synchronizer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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