ZL30120 Data Sheet
6
Zarlink Semiconductor Inc.
Pin Description
Pin # Name
I/O
Type
Description
Input Reference
C1
B2
A3
C3
B3
B4
C4
A4
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
I
d
Input References (LVCMOS, Schmitt Trigger). These are input references
available to both DPLL1 and DPLL2 for synchronizing output clocks. All eight
input references can be automatically or manually selected using software
registers. These pins are internally pulled down to Vss.
B1
A1
A2
sync0
sync1
sync2
I
d
Frame Pulse Synchronization References (LVCMOS, Schmitt Trigger).
These are the frame pulse synchronization inputs associated with input
references 0, 1 and 2. These inputs accept frame pulses in a clock format (50%
duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns.
These pins are internally pulled down to V
ss.
Output Clocks and Frame Pulses
D10 apll_clk0 O APLL Output Clock 0 (LVCMOS). This output can be configured to provide any
one of the available SONET/SDH clock outputs up to 77.76 MHz, or 25 MHz and
50 MHz. The default frequency for this output is 77.76 MHz.
G10 apll_clk1 O APLL Output Clock 1 (LVCMOS). This output can be configured to provide any
one of the available SONET/APLL clock outputs up to 77.76 MHz, or 25 MHz and
50 MHz. The default frequency for this output is 19.44 MHz.
E10 apll_fp0 O APLL Output Frame Pulse 0 (LVCMOS). This output can be configured to
provide virtually any style of output frame pulse synchronized with an associated
APLL output clock. The default frequency for this frame pulse output is 8 kHz.
F10 apll_fp1 O APLL Output Frame Pulse 1 (LVCMOS). This output can be configured to
provide virtually any style of output frame pulse synchronized with an associated
APLL output clock. The default frequency for this frame pulse output is 2 kHz.
K9 p0_clk0 O Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 100 MHz in
addition to 2 kHz. The default frequency for this output is 2.048 MHz.
K7 p0_clk1 O Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is a
programmable clock output configurable as a multiple or division of the p0_clk0
frequency within the range of 2 kHz to 100 MHz. The default frequency for this
output is 8.192 MHz.
K8 p0_fp0 O Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz.
J7 p0_fp1 O Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz.
