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MAX1148BEUP+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
______________________________________________________________________________________ 19
Method 1 allows the direct application of an external
reference from 1.5V to V
DD
+ 50mV. The REF input
impedance is typically 10kΩ. During conversion, an
external reference at REF must deliver up to 210µA and
have an output impedance less than 10Ω. Bypass REF
with a 0.1µF capacitor to AGND to improve its output
impedance.
Method 2 utilizes the internal reference buffer to reduce
the external reference load. The REFADJ input imped-
ance is typically 20kΩ. During a conversion, an external
reference at REFADJ must deliver at least 100µA and
have an output impedance less than 100Ω. The
MAX1146/MAX1148 reference buffer has a 3.277V/V
gain and the MAX1147/MAX1149 has a gain of
2.000V/V. The external reference voltage at REFADJ
multiplied by the reference buffer gain is the SAR ADC
reference voltage. This reference appears at REF and
must be from 1.5V to V
DD
+ 50mV. Bypass REFADJ
with a 0.01µF capacitor and bypass REF with a 2.2µF
capacitor to AGND.
Transfer Function
Table 7 shows the full-scale voltage ranges for unipolar
and bipolar modes.
Output data coding for the MAX1146–MAX1149 is bina-
ry in unipolar mode and two’s complement binary in
bipolar mode with 1 LSB = (V
REF
/2
N
), where N is the
number of bits (14). Code transitions occur halfway
between successive-integer LSB values. Figure 14 and
Figure 15 show the input/output (I/O) transfer functions
for unipolar and bipolar operations, respectively.
Serial Interfaces
The MAX1146–MAX1149 feature a serial interface that
is fully compatible with SPI, QSPI, and MICROWIRE. If a
serial interface is available, establish the CPU’s serial
interface as a master, so that the CPU generates the
serial clock for the ADCs. Select a clock frequency up
to 2.1MHz.
SPI and MICROWIRE Interface
When using an SPI (Figure 16a) or MICROWIRE interface
(Figure 16b), set CPOL = CPHA = 0. Two 8-bit readings
are necessary to obtain the entire 14-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
Figure 12. External Reference Applied to REF
Figure 13. Reference Adjust Circuit
UNIPOLAR MODE BIPOLAR MODE
INPUT AND OUTPUT
MODES
ZERO SCALE FULL SCALE
NEGATIVE FULL
SCALE
ZERO SCALE
POSITIVE FULL
SCALE
Single-Ended Mode V
COM
V
REF
+ V
COM
V
COM
Differential Mode V
IN-
V
REF
+ V
IN-
V
IN-
Table 7. Full Scale and Zero Scale
Note: The common mode range for the analog inputs is from AGND to V
DD
.
−
+
V
V
REF
COM
2
−
+ −
V
V
REF
IN
2
+
+
V
V
REF
COM
2
+
+
−
V
V
REF
IN
2
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
20 ______________________________________________________________________________________
edge and is clocked into the µP on SCLK’s rising edge.
The first 8-bit data stream contains the first 8-bits of
DOUT starting with the MSB. The second 8-bit data
stream contains the remaining 6 result bits.
QSPI Interface
Using the high-speed QSPI interface (Figure 17) with
CPOL = 0 and CPHA = 0, the MAX1146–MAX1149 sup-
port a maximum f
SCLK
of 2.1MHz. One 16-bit reading is
necessary to obtain the entire 14-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the µP on SCLK’s rising edge.
The first 14 bits are the data.
PIC16/PIC17 SSP Module Interface
The MAX1146–MAX1149 are compatible with a
PIC16/PIC17 microcontroller (µC), using the synchro-
nous serial-port (SSP) module. To establish SPI com-
munication, connect the controller as shown in Figure
18 and configure the PIC16/PIC17 as system master.
Initialize the synchronous serial-port control register
(SSPCON) and synchronous serial-port status register
(SSPSTAT) to the bit patterns shown in Tables 8 and 9.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data
to be synchronously transmitted and received simulta-
neously. Two consecutive 8-bit readings are necessary
to obtain the entire 14-bit result from the ADC. DOUT
data transitions on the serial clock’s falling edge and is
clocked into the µC on SCLK’s rising edge. The first 8-
bit data stream contains the first 8 data bits starting
with the MSB. The second data stream contains the
remaining bits, D5 through D0.
Figure 14. Unipolar Transfer Function
Figure 15. Bipolar Transfer Function
Figure 16a. SPI Connections
Figure 16b. MICROWIRE Connections
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
______________________________________________________________________________________ 21
Figure 17. QSPI Connections
Figure 18. SPI Interface Connection for a PIC16/PIC17
Controller
CONTROL BIT
PICI6/PICI7
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL Bit 7 X Write collision detection bit.
SSPOV Bit 6 X Receive overflow detect bit.
SSPEN Bit 5 1
Synchronous serial port enable bit:
0: Disables serial port and configures these pins as I/O port pins.
1: E nab l es ser i al p or t and confi g ur es S C K, S D O, and S C I p i ns as ser i al - p or t p i ns.
CKP Bit 4 0 Clock polarity select bit. CKP = 0 for SPI master mode selection.
SSPM3 Bit 3 0
SSPM2 Bit 2 0
SSPM1 Bit 1 0
SSPM0 Bit 0 1
Synchronous serial port mode select bit. Sets SPI master mode and selects
F
CLK
= f
OSC
/ 16.
Table 8. Detailed SSPCON Register Content
CONTROL BIT
MAX1146–MAX1149
SETTINGS
SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SMP Bit 7 0
SPI data input sample phase. Input data is sampled at the middle of the data
output time.
CKE Bit 6 1
SPI clock edge select bit. Data is transmitted on the rising edge of the serial
clock.
D/A Bit 5 X Data address bit.
P Bit 4 X Stop bit.
S Bit 3 X Start bit.
R/W Bit 2 X Read/write bit information.
UA Bit 1 X Update address.
BF Bit 0 X Buffer full status bit.
Table 9. Detailed SSPSTAT Register Content
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

MAX1148BEUP+T

Mfr. #:
Buy MAX1148BEUP+T
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 14-Bit 8Ch 116ksps 5V Precision ADC
Lifecycle:
New from this manufacturer.
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