MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
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Note 1: Tested at V
DD
= 3.0V (MAX1147/MAX1149) or 5.0V(MAX1146/MAX1148); V
COM
= 0; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Offset nulled. Measured with external reference.
Note 4: “On” channel grounded; full-scale 1kHz sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. (See
Figures 8–11.)
Note 6: The common-mode range for the analog inputs is from AGND to V
DD
.
Note 7: Digital inputs equal V
DD
or DGND.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: Measured as (V
FS
x 3.6V) - (V
FS
x 2.7V) for the MAX1147/MAX1149 and (V
FS
x 5.25V) - (V
FS
x 4.75V) for the
MAX1146/MAX1148. V
DD
= 3.6V to 2.7V for MAX1147/MAX1149 and V
DD
= 5.25V to 4.75V for the MAX1146/MAX1148.
TIMING CHARACTERISTICS
(V
DD
= 4.75V to 5.25V (MAX1146/MAX1148), V
DD
= 2.7V to 3.6V (MAX1147/MAX1149), SHDN = V
DD
, V
COM
= 0, f
SCLK
= 2.1MHz,
external clock (50% duty cycle), 18 clocks/conversion (116ksps), V
REFADJ
= V
DD
, C
REF
= 2.2µF, external +4.096V reference at REF
for the MAX1146/MAX1148, external 2.500V reference at REF for the MAX1147/MAX1149, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Typical values are at T
A
= +25°C.) (Figures 1, 2, and 3)
DIN to SCLK Setup Time t
DS
50 ns
DIN to SCLK Hold Time t
DH
0ns
SCLK Fall to Output Data Valid t
DOV
C
LOAD
= 50pF 10 80 ns
CS Fall to DOUT Enable t
DOE
C
LOAD
= 50pF 120 ns
CS Rise to DOUT Disable t
DOD
C
LOAD
= 50pF 120 ns
SHDN Rise CS Fall to SCLK Rise
Time
t
CSS
50 ns
SHDN Rise CS Fall to SCLK Rise
Hold Time
t
CSH
50 ns
External clock mode 0.1 2.1
SCLK Clock Frequency f
SCLK
Internal clock mode 0 2.1
