MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
22 ______________________________________________________________________________________
TMS32OLC3x Interface
Figure 19 shows an application circuit to interface the
MAX1146–MAX1149 to the TMS320 in external clock
mode. The timing diagram for this interface circuit is
shown in Figure 20. Use the following steps to initiate a
conversion in the MAX1146–MAX1149 and to read the
results:
1) The TMS320 should be configured with CLKX
(transmit clock) as an active-high output clock and
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
connected together with the MAX1146–MAX1149
SCLK input.
2) Drive the CS of the MAX1146–MAX1149 low
through the XF_ I/O port of the TMS320 to clock
data into the MAX1146–MAX1149 DIN.
3) Write an 8-bit word (1XXXXX11) to the
MAX1146–MAX1149 to initiate a conversion and
place the device into external clock mode. Refer to
Table 1 to select the proper XXXXX bit values for
your specific application.
4) The MAX1146–MAX1149 SSTRB output is moni-
tored by the FSR input of the TMS320. A falling
edge on the SSTRB output indicates that the con-
version is in progress and data is ready to be
received from the MAX1146–MAX1149.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 14-bit conversion result followed by 2
trailing bits, which should be ignored.
6) Pull CS high to disable the MAX1146–MAX1149
until the next conversion is initiated.
Layout, Grounding, and Bypassing
Careful PC board layout is essential for best system
performance. Boards should have separate analog and
digital ground planes. Ensure that digital and analog
signals are separated from each other. Do not run ana-
log and digital (especially clock) lines parallel to one
another, or digital lines underneath the device pack-
age.
Figure 4 shows the recommended system ground con-
nections. Establish an analog ground point at AGND
and a digital ground point at DGND. Connect all analog
grounds to the star analog ground. Connect the digital
grounds to the star digital ground. Connect the digital
ground point to the analog ground point directly at the
device. For lowest noise operation, the ground return to
the star ground’s power supply should be low imped-
ance and as short as possible.
Figure 19. MAX1146–MAX1149-to-TMS320 Serial Interface
SCLK
DIN
SSTRB
DOUT
START SEL2 SEL1 SEL0 PD1 PD0
MSB B12 B1 LSB
HIGH-Z
HIGH-Z
CS
SGL/DIF
UNI/BIP
Figure 20. TMS320 Serial-Interface Timing Diagram
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
______________________________________________________________________________________ 23
High-frequency noise in the V
DD
power supply degrades
the device’s high-speed performance. Bypass the sup-
ply to the digital ground with 0.1µF and 4.7µF capacitors.
Minimize capacitor lead lengths for best supply-noise
rejection. Connect a 10 resistor in series with the 0.1µF
capacitor to form a lowpass filter when the power supply
is noisy.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1146–MAX1149
are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (t
AJ
) is the sample-to-sample variation in
the time between the samples. Aperture delay (t
AD
) is
the time between the rising edge of the sampling clock
and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the ENOB as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V
1
is the fundamental amplitude, and V
2
through
V
5
are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component.
Chip Information
TRANSISTOR COUNT: 5589
PROCESS: BiCMOS
THD
VVVV
V
log
+++
20
2
2
3
2
4
2
5
2
1
Revision History
Pages changed at Rev 2: 1, 20, 23, 25.
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
24 ______________________________________________________________________________________
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
V
DD
SCLK
DINCH3
CH1
CH0
TOP VIEW
SSTRB
DOUT
DGND
AGNDN.C.
N.C.
N.C.
N.C.
12
11
9
10
REFADJ
REF
COM
MAX1146
MAX1147
TSSOP
SHDN
CS
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
V
DD
SCLK
DINCH3
CH2
CH1
CH0
SSTRB
DOUT
DGND
AGNDCH7
CH6
CH5
CH4
12
11
9
10
REFADJ
REF
COM
MAX1148
MAX1149
TSSOP
SHDN
CS
CH2
Pin Configurations

MAX1148BEUP+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 14-Bit 8Ch 116ksps 5V Precision ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union