9FG830AFLF Datasheet 9FG830AGILF, 9FG830AFILFT, 9FG830AGLFT | P10-P12

IDT

Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17

9FG830

Eight Output Differential Frequency Generator for PCIe Gen3 and QPI

Differential Clock Tolerances x1 - 25MHz

Clock Periods - Differential Outputs with Spread Spectrum Disabled

1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock

-c2c jitter

AbsPer

Min

-SSC

Short-Term

Average

Min

- ppm

Long-Term

Average

Min

0 ppm

Period

Nominal

+ ppm

Long-Term

Average

Max

+SSC

Short-

Term

Average

Max

+c2c jitter

AbsPer

Max

0 100.00 9.95000 10.00000 10.00000 10.00000 10.05000 ns 1,2

0 125.00 7.95000 8.00000 8.00000 8.00000 8.05000 ns 1,2

0 133.33 7.45000 7.50000 7.50000 7.50000 7.55000 ns 1,2

10 166.67 5.94994 5.99994 6.00000 6.00006 6.05006 ns 1,2

0 200.00 4.95000 5.00000 5.00000 5.00000 5.05000 ns 1,2

6 266.67 3.69998 3.74998 3.75000 3.75002 3.80002 ns 1,2

10 333.33 2.94997 2.99997 3.00000 3.00003 3.05003 ns 1,2

0 400.00 2.45000 2.50000 2.50000 2.50000 2.55000 ns 1,2

Clock Periods - Differential Outputs with Spread Spectrum Enabled

1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock

-c2c jitter

AbsPer

Min

-SSC

Short-Term

Average

Min

- ppm

Long-Term

Average

Min

0 ppm

Period

Nominal

+ ppm

Long-Term

Average

Max

+SSC

Short-

Term

Average

Max

+c2c jitter

AbsPer

Max

96 99.75 9.94910 9.99910 10.02410 10.02506 10.02603 10.05103 10.10103 ns 1,2

19 124.69 7.94990 7.99990 8.01990 8.02005 8.02020 8.04020 8.09020 ns 1,2

96 133.00 7.44933 7.49933 7.51808 7.51880 7.51952 7.53827 7.58827 ns 1,2

10 166.25 5.94998 5.99998 6.01498 6.01504 6.01510 6.03010 6.08010 ns 1,2

96 199.50 4.94955 4.99955 5.01205 5.01253 5.01301 5.02551 5.07551 ns 1,2

-98 266.00 3.70039 3.75039 3.75977 3.75940 3.75903 3.76841 3.81841 ns 1,2

10 332.50 2.94999 2.99999 3.00749 3.00752 3.00755 3.01505 3.06505 ns 1,2

96 399.00 2.44978 2.49978 2.50603 2.50627 2.50651 2.51276 2.56276 ns 1,2

Guaranteed by design and characterization, not 100% tested in production.

DIF

All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to the exact target XTAL

frequency.

Notes

Measurement Window

Units

SSC ON

-0.5%

Down

Spread

Center

Freq.

MHz

Notes

Measurement Window

Units

Center

Freq.

MHz

Synthesis

Error

(ppm)

SSC OFF

or SSC +/-

0.25%

Center

Spread

Synthesis

Error

(ppm)

DIF

IDT

Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17

9FG830

Eight Output Differential Frequency Generator for PCIe Gen3 and QPI

Differential Clock Tolerances x1 - 14.31818MHz

Clock Periods - Differential Outputs with Spread Spectrum Disabled

1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock

-c2c jitter

AbsPer

Min

-SSC

Short-Term

Average

Min

- ppm

Long-Term

Average

Min

0 ppm

Period

Nominal

+ ppm

Long-Term

Average

Max

+SSC

Short-

Term

Average

+c2c jitter

AbsPer

Max

35 100.00 9.94965 9.99965 10.00000 10.00035 10.05035 ns 1,2

-114 125.00 7.95091 8.00091 8.00000 7.99909 8.04909 ns 1,2

35 133.33 7.44974 7.49974 7.50000 7.50026 7.55026 ns 1,2

-104 166.67 5.95062 6.00062 6.00000 5.99937 6.04937 ns 1,2

35 200.00 4.94983 4.99983 5.00000 5.00018 5.05018 ns 1,2

42 266.67 3.69984 3.74984 3.75000 3.75016 3.80016 ns 1,2

-104 333.33 2.95031 3.00031 3.00000 2.99969 3.04969 ns 1,2

35 400.00 2.44991 2.49991 2.50000 2.50009 2.55009 ns 1,2

Clock Periods - Differential Outputs with Spread Spectrum Enabled

1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock

-c2c jitter

AbsPer

Min

-SSC

Short-Term

Average

Min

- ppm

Long-Term

Average

Min

0 ppm

Period

Nominal

+ ppm

Long-Term

Average

Max

+SSC

Short-

Term

Average

+c2c jitter

AbsPer

Max

199 99.75 9.94807 9.99807 10.02307 10.02506 10.02706 10.05206 10.10206 ns 1,2

-100 124.69 7.95085 8.00085 8.02085 8.02005 8.01925 8.03925 8.08925 ns 1,2

199 133.00 7.44855 7.49855 7.51730 7.51880 7.52029 7.53904 7.58904 ns 1,2

10 166.25 5.94998 5.99998 6.01498 6.01504 6.01510 6.03010 6.08010 ns 1,2

199 199.50 4.94903 4.99903 5.01153 5.01253 5.01353 5.02603 5.07603 ns 1,2

-140 266.00 3.70055 3.75055 3.75992 3.75940 3.75887 3.76825 3.81825 ns 1,2

10 332.50 2.94999 2.99999 3.00749 3.00752 3.00755 3.01505 3.06505 ns 1,2

199 399.00 2.44952 2.49952 2.50577 2.50627 2.50676 2.51301 2.56301 ns 1,2

Guaranteed by desi

n and characterization, not 100% tested in production.

Center

Freq.

MHz

Synthesis

Error

(ppm)

SSC OFF

or SSC +/-

0.25%

Center

Spread

Synthesis

Error

(ppm)

DIF

All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to the exact target XTAL

frequency.

Notes

Measurement Window

Units

SSC ON

-0.5%

Down

Spread

Center

Freq.

MHz

Notes

Measurement Window

Units

IDT

Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17

9FG830

Eight Output Differential Frequency Generator for PCIe Gen3 and QPI

General SMBus serial interface information for the 9FG830

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address DC

(H)

• IDT clock will

acknowledge

• Controller (host) sends the begining byte location = N

• IDT clock will

acknowledge

• Controller (host) sends the data byte count = X

• IDT clock will

acknowledge

• Controller (host) starts sending

Byte N through

Byte N + X -1

(see Note 2)

• IDT clock will

acknowledge

each byte

one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address DC

(H)

• IDT clock will

acknowledge

• Controller (host) sends the begining byte

location = N

• IDT clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address DD

(H)

• IDT clock will

acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends

Byte N + X -1

• IDT clock sends

Byte 0 through byte X (if X

(H)

was written to byte 8)

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

IDT (Slave/Receiver)

ACK

PstoP bit

X Byte

Index Block Write Operation

Slave Address DC

(H)

Beginning Byte = N

WRite

starT bit

Controller (Host)

Byte N + X - 1

Data Byte Count = X

Beginning Byte N

T starT bit

WR WRite

RT Repeat starT

RD ReaD

Beginning Byte N

Byte N + X - 1

N Not acknowledge

PstoP bit

Slave Address DD

(H)

Index Block Read Operation

Slave Address DC

(H)

Beginning Byte = N

ACK

Data Byte Count = X

ACK

IDT (Slave/Receiver)

Controller (Host)

X Byte

ACK

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

9FG830AFLF

Mfr. #:

Buy 9FG830AFLF

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner PCIE SYNTHESIZER - GEN3, 8 OUTPUT

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

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9FG830AFLF

9FG830AFLF

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