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9FG830AFLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
IDT
®
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
13
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Pin # Name Control Function T
yp
e0 1Default
Bit 7
RW Pin 27
Bit 6
RW Pin 5
Bit 5
RW Pin 44
Bit 4
RW Pin 7
Bit 3
RW Off On Pin 26
Bit 2
RW
Hardware
Select
Software
Select
0
Bit 1
RW Driven Hi-Z 0
Bit 0
RW Down Center 0
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
SMBus Table: Output Enable Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7
DIF_7 EN Output Enable RW Disable Enable 1
Bit 6
DIF_6 EN Output Enable RW Disable Enable 1
Bit 5
DIF_5 EN Output Enable RW Disable Enable 1
Bit 4
DIF_4 EN Output Enable RW Disable Enable 1
Bit 3
DIF_3 EN Output Enable RW Disable Enable 1
Bit 2
DIF_2 EN Output Enable RW Disable Enable 1
Bit 1
DIF_1 EN Output Enable RW Disable Enable 1
Bit 0
DIF_0 EN Output Enable RW Disable Enable 1
Note:
SMBus Table: Output Stop Mode Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7
DIF_7 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 6
DIF_6 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 5
DIF_5 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 4
DIF_4 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 3
DIF_3 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 2
DIF_2 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 1
DIF_1 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
Bit 0
DIF_0 STOP EN Free Run/ Stop Enable RW Free-run Stop-able 0
44
7
B
y
te 0
27
5
26
Spread Enable
1
-
Enable Software Control of Frequency,
Spread Enable (Spread Type always
Software Control)
- DIF_STOP# drive mode
- Spread Type
B
y
te 1
-
-
-
-
-
-
-
-
B
y
te 2
-
-
Byte 1 sets outputs active or inactive, not the conditons set by the OE inputs.
-
-
-
-
See Frequency
Selection Table.
FS3
1
FS2
1
FS1
1
FS0
1
-
-
IDT
®
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
14
SMBus Table: Frequency Select Readback Register
Pin # Name Control Function Type 0 1 Default
Bit 7
SEL14M_25M#
1
State of pin 27 R Pin 27
Bit 6
FS2
1
State of pin 6 R Pin 6
Bit 5
FS1
1
State of pin 44 R Pin 44
Bit 4
FS0
1
State of pin 45 R Pin 45
Bit 3
SPREAD
1
State of pin 26 R Off On Pin 26
Bit 2
RX
Bit 1
RX
Bit 0
RX
Notes:
1. These bits reflect the state of the corresponding pins, regardless of whether software
programming is enabled or not.
SMBus Table: Vendor & Revision ID Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7
RID3 R - - X
Bit 6
RID2 R - - X
Bit 5
RID1 R - - X
Bit 4
RID0 R - - X
Bit 3
VID3 R - - 0
Bit 2
VID2 R - - 0
Bit 1
VID1 R - - 0
Bit 0
VID0 R - - 1
SMBus Table: DEVICE ID
Pin # Name Control Function T
yp
e0 1Default
Bit 7
DEVID7 R 0
Bit 6
DEVID6 R 0
Bit 5
DEVID5 R 0
Bit 4
DEVID4 R 1
Bit 3
DEVID3 R 0
Bit 2
DEVID2 R 0
Bit 1
DEVID1 R 0
Bit 0
DEVID0 R 0
SMBus Table: Byte Count Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7
BC7 RW - - 0
Bit 6
BC6 RW - - 0
Bit 5
BC5 RW - - 0
Bit 4
BC4 RW - - 0
Bit 3
BC3 RW - - 0
Bit 2
BC2 RW - - 1
Bit 1
BC1 RW - - 1
Bit 0
BC0 RW - - 1
See Frequency
Selection Table.
B
y
te 6
-
-
-
-
-
-
-
Writing to this register
will configure how many
bytes will be read back,
default is 07
= 7 bytes.
-
-
-
-
-
VENDOR ID
-
-
-
-
-
B
y
te 5
-
-
-
B
y
te 4
-
REVISION ID
-
-
-
Reserved Reserved
Reserved Reserved
26
Reserved Reserved
45
44
Byte 3
6
27
Device ID = 10 hex
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IDT
®
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
15
SMBus Table: Reserved Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
SMBus Table: Reserved Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
SMBus Table: M/N Programming Enable
Pin # Name Control Function T
yp
e0 1Default
Bit 7
M/N_EN
PLL M/N Programming
Enable
RW Disable Enable 0
Bit 6
OE_Polarity
Select Polarity of OE
inputs
RW OE# OE
1
Bit 5
REFOUT_En
Enables/Disables REF RW Disable Enable
1
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: PLL Frequency Control Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7
PLL N Div8 N Divider Prog bit 8 RW X
Bit 6
PLL N Div9 N Divider Prog bit 9 RW X
Bit 5
PLL M Div5 RW X
Bit 4
PLL M Div4 RW X
Bit 3
PLL M Div3 RW X
Bit 2
PLL M Div2 RW X
Bit 1
PLL M Div1 RW X
Bit 0
PLL M Div0 RW X
B
y
te 10
-
The decimal
representation of M and
N Divider in Byte 11 and
12 will configure the PLL
VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency
= fXTAL x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
-
-
M Divider Programming
bit (5:0)
-
-
-
-
-
5
Reserved
B
y
te 9
-
-
Reserved
Reserved
Reserved
Reserved
B
y
te 7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
B
y
te 8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

9FG830AFLF

Mfr. #:
Buy 9FG830AFLF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PCIE SYNTHESIZER - GEN3, 8 OUTPUT
Lifecycle:
New from this manufacturer.
Delivery:
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