IDT
®
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI 1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
6
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
T
A
= T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate Trf Scope averaging on 1 4
V/ns
1, 2, 3
Slew rate matchin
∆
Trf Slew rate matchin
, Scope avera
in
on 20
%
1, 2, 4
Voltage High VHigh 660 850 1
Voltage Low VLow -150 150 1
Max Volta
eVmax 1150 1
Min Volta
e Vmin -300 1
Vswing Vswing Scope averaging off 300 mV 1, 2
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 550 mV 1, 5
Crossing Voltage (var)
∆
-Vcross Scope averaging off 140 mV 1, 6
2
Measured from differential waveform
6
The total variation of all Vcross measurements in a particular system. This is a subset of V_cross_min/max (V_cross absolute)
allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Measurement on single ended signal using
absolute value. (Scope avera
in
off)
mV
1
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA.
I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
(100
Ω
differential impedance).
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscillosco
e uses for the ed
e rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
Electrical Characteristics - Current Consumption
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
I
DD3.3
VDD, All outputs active @100MHz
250
mA 1
I
DDA3. 3OP
VDDA, All outputs active @100MHz
28
mA 1
I
DD3.3
VDD, All outputs active @400MHz
200
mA 1
I
DDA3. 3OP
VDDA, All outputs active @400MHz
28
mA 1
I
DD3.3DS
VDD, All DIF pairs stopped driven 190 mA 1
I
DDA3. 3DS
VDDA, All DIF pairs stopped driven 28 mA 1
I
DD3.3DZ
VDD, All DIF pairs stopped Hi-Z 38 mA 1
I
DDA3.3DZ
VDDA, All DIF pairs stopped Hi-Z 28 mA 1
1
Guaranteed by desi
n and characterization, not 100% tested in production.
2
I
REF
= V
DD
(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
.
Operating Supply Current
DIF_STOP# Current
Electrical Characteristics - Output Duty Cycle, Jitter, and Skew Characterisitics
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle t
D
Measured differentially, PLL Mode 45 55 % 1
Skew, Output to Output t
sk3
V
T
= 50% 50 ps 1
Jitter, Cycle to cycle t
c
c-c
c
25M input 50 ps 1,3
Jitter, Cycle to cycle t
jcyc-cyc
14.318M input 60 ps 1,3
1
Guaranteed by desi
n and characterization, not 100% tested in production.
2
I
REF
= V
DD
(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
.
3
Measured from differential waveform
